Motorola Corporation

Other

Chinh H Le

James B Eifert

Wallace B Harwood, Iii

Gerald E Vauk, Jr

Oded Yishay

Jay A Hartvigsen

Michael E Gladden

Ann E Harwood

Basil J Jackson

Terry E Downs

Accordingly, the present invention provides a method for synchronously accessing memory in order to improve the performance in systems which use memories with slower cores. A first address for a first memory access is provided during a first clock period. A first control signal to indicate an address phase of the first memory access is activated during the first clock period. A second control signal to indicate a data phase of the first memory access is activated during a second clock period subsequent to the first clock period. A first data element accessed by the first address is received during a third clock period immediately subsequent to the second clock period. A second address for a second memory access is provided during the third clock period. The first control signal indicating an address phase of the second memory access is activated during the third clock period.

Method for accessing memory using overlapping accesses and early

A method and apparatus for providing an external indication of internal cycles in a data processing system (10) in order to more easily debug software being executed by data processing system (10). In one embodiment, data processing system (10) provides cycle type signals (14) external to data processing system (10). The cycle type signals (14) can be used to determine a variety of information about the activity and bus cycles being performed within data processing system (10), activity which is not readily discernible except by way of the cycle type signals (14). In some cases the information provided by the cycle type signals (14) is sufficient for debug purposes; in other cases, information from additional signals, e.g. the address type signals (15) and the read/write signal (19) may also be required.

Method and apparatus for providing an external indication of internal

An integrated circuit microprocessor (30) accesses external memory using internally-generated control signals having programmable memory access interface types. A register (61), associated with a memory region, stores an encoded value. During an access to that memory region, a decoder (63) decodes the encoded value to provide a decoded signal. If the decoded signal is in a legal state, then an access controller (64) activates external control signals with timing corresponding to the legal state. If the decoded signal is in a reserved state, then the access controller (64) prevents the access from taking place by keeping the external control signals inactive, preventing software errors from resulting in illegal accesses. For one legal memory access type, the early synchronous output enable access type, the access controller (64) activates an output enable signal at a clock transition but doesn't latch the corresponding data until the next transition, allowing efficient accesses to memory devices with slower memory cores.

Integrated circuit microprocessor with programmable memory access

Method and apparatus in a data processing system (10) for selectively inserting bus cycle idle time. The present invention allows a data processing system (10) to selectively insert a predetermined number of idle clocks at the end of a bus cycle. In one embodiment of the present invention, there is a base register (48) and an option register (46) corresponding to each one of the chip select terminals (73). In one embodiment of the present invention, each option register (46) includes a user programmable idle control bit (110). If a first chip select is used to select a peripheral device during a bus cycle to that same peripheral device, the idle control bit (110) which corresponds to the first chip select determines whether or not one or more idle clocks will be inserted after that bus cycle.

Method and apparatus in a data processing system for selectively

A data processor (21) includes an external bus interface circuit (33) responsive to two internal bus master devices (30, 34) to perform either a fixed or a variable burst access. The data processor (21) activates an external control signal to indicate whether a burst access is a fixed or a variable burst access. The data processor (21) indicates the port size of the accessed memory region by providing a port size signal to the external bus interface circuit (33). The external bus interface circuit (33) is responsive to the port size signal to break up the burst cycle into two or more burst cycles on the external bus (22, 23), if the accessed location corresponds to a memory (24) with a different port size than the internal bus (31).

Data processor with controlled burst memory accesses and method therefor

A data processor (30) includes a multi-level protection circuit (50) which enables the generation of external control signals. The multi-level protection circuit (50) defines regions of protection (41, 42), which may be nested. The protection circuit (50) checks access cycle attributes such as read or write, supervisor or user, and data or instruction. First (51) and second (54) decoders are associated with each other and define two regions (41, 42) which may overlap. When a CPU (31) accesses a memory location within both regions, the protection attributes of the second decoder (54), at a higher priority level than the first decoder (51), control. If an attempted access violates the programmable protection attributes of the second region (42), then the multi-level protection circuit (50) prevents the access from occurring, even though the access attributes of the first decoder (51) alone would enable the access. The protection circuit (50) thus allows the use of high-density memory or peripheral devices for multiple purposes.

Data processor with a multi-level protection mechanism, multi-level

A modular chip select control circuit (80) is scalable by having an address decode stage (90) with a first number of address decoders, a control stage (100) with a second number of control units, and a pin configuration stage (110) with a third number of pin configuration logic circuits. These three numbers, defining the number of memory regions, the access pipeline depth, and the number of chip select signals, respectively, are independent and may be changed between chip designs to accommodate different system needs. The control stage includes an early pipeline control circuit (186) which allows the control units (170, 180) to pipeline pending memory cycles, based on an accessed region's characteristics. The early pipeline control circuit (186) together with the control units (170, 180) enforce a set of pipelining rules to ensure data integrity and proper cycle termination, thus providing an efficient series of pipelined memory access cycles.

Modular chip select control circuit and method for performing pipelined

A pin configuration logic circuit (120) has a pin function register (130) which defines a selected pin function, such as chip enable, write enable, and output enable, to be provided as a chip select signal. The logic circuit (120) allows an arbitrary pipeline length by causing the chip select signal to obey only the timing of the active cycle. For a two-deep access pipeline, the logic circuit (120) marks whether a first or a second cycle owns the pin. The pin configuration logic circuit (120) uses the timing associated with the selected pin function to provide the chip select signal during the first cycle if the attributes of the cycle, such as an access to a region programmed in the pin function register, are met. During the second cycle, the pin configuration logic circuit (120) further obeys the timing associated with the selected pin function if the attributes of that cycle are also met.

Programmable pin configuration logic circuit for providing a chip select

An integrated circuit microprocessor (30) reads data from an external memory device (22, 23) through early overlapping memory access cycles, thus allowing efficient accesses to slower-speed memory. The microprocessor (30) drives a first address and activates a chip enable signal during a first clock period. The chip enable signal causes the external memory device to latch the first address and begin a first memory access. During a second, subsequent clock period, the microprocessor (30) provides a second address and again activates the chip enable signal. During a third clock period, subsequent to the second clock period, the microprocessor (30) latches a first data element associated with the first address. This early overlapping memory access type allows a memory device with a slow memory core to pipeline the second access prior to completion of the first access, increasing system efficiency.

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Austin, TX, United States of America

Chinh H Le