Programmable Microelectronics Corporation

Stmicroelectronics Gmbh

Winbond Electronics Corporation

Winbond Electronics North America Corporation

Ic Works, Inc.

Chinh D Nguyen

Guy S Yuen

Wei-Chan Hsu

Shang-De Ted Chang

Vishal Sarin

Vikram Kowshik

Andy Teng-Feng Yu

Francis Yu

Fred T Cheng

Li-Hsin D Lu

Chi-Tay Huang

A switching circuit includes a switch having first and second terminals coupled between a voltage supply and ground potential and having a control terminal coupled to receive a control signal indicative of the output voltage of an associated semiconductor circuit. The switch also includes an output terminal coupled to the well region within which is formed the associated semiconductor circuit. In preferred embodiments, the control signal transitions from a first state to a second state when the output voltage exceeds a predetermined potential. In response thereto, the switching circuit changes the well potential of the associated semiconductor circuit from a first voltage to ground potential, wherein the first voltage is greater than ground potential.

Method and apparatus for switching a well potential in response to an output voltage

A semiconductor memory includes cell array having a plurality of bit lines connected to respective input terminals of a column decoder. Input/output (I/O) lines are connected between respective output terminals of the column decoder and a plurality of sense circuits, where each sense circuit includes its own reference circuit, a sense amplifier, and equalizing circuit. The reference circuit includes a reference array essentially identical to the cell array and provides a reference voltage to respective first input terminals of its associated equalizing circuit and sense amplifier. Second input terminals of the equalizing circuit and sense amplifier of each sense circuit are connected to a corresponding I/O line. During read operations, the equalizing circuits are initially maintained in a conductive state so as to equalize the I/O line voltage and the reference voltages. Thereafter, the equalizing circuits transition to a non-conductive state so as to isolate the I/O line from the reference voltage. In response thereto, each I/O line voltage immediately changes to either a more positive or more negative voltage, depending on the binary state of the cell associated therewith.

Sense amplifier with improved bit line initialization

A circuit for determining an initial winding combination for motor startup of a polyphase dc motor having a transistor driver circuit comprising a plurality of high side winding drivers and low side winding drivers operably connected to first and second voltage sources comprises a current mirror circuit and a plurality of sense FETs each operably connected between one of the voltage sources and the gate of one of the winding driver transistors in each phase combination. The sense FETs are operably connected to one side of the current mirror circuit. The mirror circuit compares the current through the sense FET with a current threshold provided on the other side of the current mirror and produces an output signal when the threshold is reached. At the same time, the time to reach the threshold is measured and the phase combination having the longest time is stored. Also when the threshold is reached, the sequencer advances to the next phase combination for measurement until all phase combination have been sequenced. The motor is then started with the phase combination having the longest time measurement energized first.

Circuit and method for determining optimal phase combination for startup

A page buffer facilitates programming of a memory cell within an associated memory array by selectively connecting a bit line associated with the memory cell to a negative voltage supply in response to the logic state of a data signal. The page buffer includes an SRAM latch having first and second nodes, a cross-coupled latch having first and second nodes, and a pass transistor. The first node of the SRAM latch is coupled to receive the data signal and to a first control terminal of the cross-coupled latch. The second node of the SRAM latch is coupled to a second control terminal of the cross-coupled latch. The second node of the cross-coupled latch is coupled to a gate of the pass transistor which, in turn, is connected between the bit line and the negative voltage supply. When the data signal is in a first logic state, the cross-coupled latch turns on the pass transistor and, in connecting the bit line to the negative voltage supply, facilitates programming of the cell. When the data signal is in a second logic state, the cross-coupled latch turns off the pass transistor and allows the bit line to float which, in turn, precludes programming of the cell.

Page buffer having negative voltage level shifter

A switching circuit includes a first switch connected between a first node and a first potential, a second switch connected between the first node and a second potential levels, a third switch connected between the first node and an output terminal, and a fourth switch connected between the output terminal and a third potential. A first control signal controls the conductivity of the first and second switches, a second control signal controls the conductivity of the third switch, and a logical combination the first and second control signals controls the conductivity of the fourth switch.

Method and apparatus for switching nodes between multiple potentials

A non-volatile latch is disclosed which includes four PMOS floating gate memory cells arranged in a 2.times.2 matrix. Binary data values are written to the latch by the threshold voltage of the cells, where a first binary value is written by programming all the cells, and the second binary value is written by leaving all the cells in an erased state. Thus, since a program operation is required when writing only one of the binary value, high program voltages and floating gate charge times are eliminated when writing the other binary value. After a read operation in which the binary value stored in the cells is provided as output, this binary value is automatically latched in a latch circuit. In this manner, subsequent reads to the latch do not require accessing the cells.

Non-volatile latch having PMOS floating gate memory cells

A nonvolatile PMOS memory array includes a plurality of pages, where each column of a page includes two series-connected PMOS OR strings in parallel with a bit line. Each PMOS OR string includes a PMOS select transistor coupled between the bit line and two series connected PMOS floating gate memory cells. The PMOS floating gate memory cells are programmed via channel hot electron (CHE) injection and erased via electron tunneling. A soft-program mechanism is used to compensate for over-erasing of the memory cells. In some embodiments, the bit lines are segmented along page boundaries to increase speed.

PMOS memory array having OR gate architecture

A memory array includes a predetermined number of rows of PMOS Flash memory cells formed in each of a plurality of n- well regions of a semiconductor substrate, where each of the n- well regions defines a page of the memory array. In some embodiments, a plurality of bit lines define columns of the memory array, where the p+ drain of each of the memory cells in a common column are coupled to an associated one of the bit lines. In other embodiments, a plurality of sub-bit lines define columns of the memory array, where the p+ drain of each of the memory cells in a common column are coupled to an associated one of the sub-bit lines, and groups of a predetermined number of the sub-bit lines are selectively coupled to associated ones of a plurality of bit lines via pass transistors. During erasing operations a selected n- well region, within which are formed the memory cells of a selected page, is held at a first voltage, while the other n- well regions, within which are formed the memory cells of the respective un-selected pages, are held at a second voltage. The first and second voltages are different, thereby isolating the un-selected pages from erasing operations of the selected page.

Non-volatile memory array architecture

Arrangement for providing improved current source signals in a DAC current source circuit including a current source transistor, an output transistor, and a switching transistor for selectively grounding the source current or directing it through the output transistor. The DAC current source circuit includes a high gain double cascode device for electrically isolating the current source and output transistors from the switching transistor. The isolation device may include one, two or more transistors in series. The arrangement further includes a matching circuit at the input of the DAC current source circuit.

Digital to analog converter (DAC) current source arrangement

In a digital-to-analog converter (DAC) current source including a current mirror, an output transistor biased by a reference voltage and a steering transistor, a structure and a method are provided to implement the DAC current source without current spikes in the output current. Current spikes in the output current are avoided by including a transistor acting as a low-pass filter between the steering transistor and the output transistor. In one embodiment, the DAC current source circuit is implemented by PMOS transistors.

DAC current source with stabilizing bias

A reference generator system that operates in either a current-controlled mode or a voltage-controlled mode and includes a power-down circuit connected to the operational amplifier to power down the operational amplifier when the reference generator is switched to the current-controlled mode.

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San Jose, CA, United States of America

Chinh D Nguyen