Via Technologies, Inc.

Alpha Imaging Technology Corporation

S3 Incorporated, Inc.

Chingwo Ma

Shu-Mei Li

Chih-Chia Wang

Jeff Lin

Kai-Pon Kao

Tien-Hui Chen

Inging Yang

I-Chou Chung

Wei-Chan Hsu

Cen-Chieh Huang

Ping-Chieh Kao

Hsin-Chin Hsu

Yi-Sheng Lin

A null detector and its corresponding method are provided. The null detector includes a power detector, a smoother, and an overlapper. The power detector outputs a power level signal according to the power level of a received signal. The smoother is coupled to the power detector for determining according to the power level signal whether the received signal is transmitting a null symbol, and then the smoother outputs a null detection signal at a first state value or a second state value indicating the result of the determination. The overlapper is coupled to the smoother for providing the duration and position of the null symbols transmitted by the received signal according to the null detection signal.

Null detector and method thereof

A time domain symbol timing synchronization circuit is disclosed, which comprises: an autocorrelation function calculator for calculating cyclic prefix autocorrelation functions and an offset time estimator for searching peak positions of cyclic prefix autocorrelation functions to indicate symbol boundary of received communication symbols. The offset time estimator compares a current peak position and a previous peak position. If (a) the difference of the positions is larger than a threshold and (b) the current peak is smaller than a reference average peak, the current peak is determined as false; the offset time estimator weeds out and replaces the current peak position by the previous peak position; and the current peak is not introduced in the reference average peak calculation.

Time domain symbol timing synchronization circuit and method thereof for communication systems

A radio receiver has an ADC connected to an RF module. Baseband processing modules are connected to the ADC, and a power control module is connected to each of the baseband processing modules. Each of the baseband processing modules is capable of performing detection, demodulation, time and frequency synchronization, decoding, and de-scrambling of signals of a respective modulation format among numerous modulation formats. At least one of the baseband processing modules also has a rate converter connected to the ADC for converting a data rate of signals output from the ADC to a data rate of the corresponding modulation format of that baseband processing module. The power control module is connected to the baseband processing modules and controls power to the baseband processing modules according to signals received from the baseband processing modules.

Radio receiver supporting multiple modulation formats with a single pair of ADCs

A method for updating coefficients in a decision feedback equalizer (DFE). The DFE comprises an ISI canceler for canceling inter-symbol interference (ISI) from a plurality of first signals received from a channel. A first symbol comprising a set of the first signals is decoded to generate a decoded symbol. Then, a vector of error values computed as the difference between the decoded symbol, and the first symbol is obtained. According to the decoded symbol and the vector of the error values, a temp matrix is generated. Next, the values of the elements in every diagonal line of the temp matrix are averaged. Finally, the coefficients are updated by the Toeplitz Matrix.

Method for updating coefficients in decision feedback equalizer

A conversion system and method is disclosed for converting between digital and analog data signals. The conversion system comprises a signal input line for each digital data signal, a reconstructor-resampler unit for each digital data signal, a combiner, a modulator, a digital-to-analog converter, and a signal output line. Each signal line input couples to the respective reconstructor-resampler unit for the digital data signal. Each reconstructor-resampler unit then couples to a combiner which couples to a modulator. The modulator couples to the digital-to-analog converter that couples to the signal output line from which an analog output signal is produced. The reconstructor-resampler comprises a sampling member coupled to the signal line input and a polynomial interpolator member coupled to the sampling member and the modulator. Also, the modulator operates at a predetermined, or fixed, frequency regardless of the sampling frequency of the digital data signal. The steps of the conversion method include inputting a digital data signal having a sampling frequency, reconstructing and resampling the digital data signal to generate a resampled data signal, performing noise-shaping on the resampled data signal to generate a x-bit data signal from a modulator operating at a predetermined frequency regardless of the sampling frequency of any of the digital data signals, and converting the x-bit data signal to an analog data signal. In addition, an analog-to-digital conversion system and method is disclosed that comprises a signal line input, a decimator, a reconstructor-resampler a signal output line, and a modulator operating at a predetermined frequency to convert an analog data signal to a digital data signal.

Sigma-delta digital-to-analog conversion system and process through

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Danville, CA, United States of America

Chingwo Ma