Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Worldwide Semiconductor Manufacturing Corporation

Semiconductor Manufacturing Corp.

Chingfu Lin

Ling-Sung Wang

Chien-Jung Wang

Hsueh-Chung Chen

I-Hsiung Huang

Lien-Jung Hung

Dahcheng Lin

Anseime Chen

Yi-Fang Cheng

Ching-Lang Yen

A substrate having a conductive layer is provided. A dielectric layer is then formed above the conductive layer. At least one via hole is then formed in the dielectric layer, to expose a portion of the conductive layer. The conductive layer is then covered with a gap fill polymer layer, to completely fill the via hole. A chemical mechanical polishing step is performed to remove the partial gap fill polymer layer on the outside of the via hole. An etching step, is performed to remove a portion of partial gap fill polymer layer remaining in the via hole, resulting in a partial gap fill polymer. A lithographic process is conducted to form a patterned photoresist layer over the dielectric layer. The photoresist layer has an opening that exposes the via hole and partial gap fill polymer. A portion of the dielectric layer exposed by the opening is etched away, to form a trench in the dielectric layer. The photoresist layer and the partial fill polymer layer are then removed, to expose a part of the conductive layer. The via hole and trench are filled with metal material, to form a plug and line simultaneously.

Dual damascene partial gap fill polymer fabrication process

A method of planarizing an oxide layer. The method includes performing an isotropic chemical dry etching operation using a nitrogenous processing gas. Furthermore, oxygen can also be added to the nitrogenous processing gas during the isotropic chemical dry etching operation. In addition, the nitrogenous processing gas can be nitrogen or a nitrogen-oxygen compound, where the nitrogen-oxygen compound can be nitrogen monoxide, nitrogen dioxide or nitrous oxide.

Method for planarizing an oxide layer

A method of forming a multiple layer damascene structure. A substrate comprising of a multi-layered stack that includes, from bottom to top, a metallic layer, a first etching stop layer, a first dielectric layer, a second etching stop layer and a second dielectric layer is provided. A photoresist layer having large area openings and vias pattern is formed over the substrate. Large area openings and vias that expose a portion of the first etching stop layer are formed in the substrate. A barrier layer that fills all the large area openings and vias is formed over the substrate. Chemical-mechanical polishing is conducted to remove a portion of the barrier layer and expose the second dielectric layer. A second photoresist having a trench pattern thereon is formed over the substrate. Using the second photoresist as a mask, etching is conducted so that the second etching stop layer around the vias is exposed. Lastly, the barrier layer is removed.

Method of forming dual damascene structure

A method for planarizing a polysilicon layer is described. A polysilicon layer is etched with an oxygen-based gas and a halogen-based gas. The oxygen-based gas comprises an nitrogen oxide oxygen gas. The nitrogen oxide gas includes NO, NO,, N,O, or the combination thereof. The halogen-based gas includes a F, Cl, Br., I, NF,, SF,, Cl,, HCl, SiCl,, fluorocarbon, or a combination thereof. The fluorocarbon includes CF,, CHF,, CH,F,, CH,F, or the like.

Method and planarizing polysilicon layer

A method of protecting a tungsten plug from corroding. After a tungsten plug is formed in a substrate, a wire is formed on the substrate to couple with the tungsten plug. The substrate is dipped into an electrolyte solution. The electrolyte solution is acid or alkaline enough to discharge charges accumulated on the wire. Then, a wet cleaning process is performed to remove polymer formed on the wire.

Method of protecting tungsten plug from corroding

A method of forming a shallow trench isolation structure is described. A mask layer and a photoresist layer with an opening are formed on a substrate in sequence. The photoresist layer serves as an etching mask, and then a portion of the mask layer and a portion of the substrate are etched to form a trench in the substrate. A portion of the photoresist layer is removed, and the opening is in-situ widened. Then, a portion of the mask layer exposed by the widened opening is removed. In addition, a top corner of the trench is rounded after removing the portion of the mask layer. Finally, the trench is filled with an insulation material to form a shallow trench isolation structure.

Method of forming shallow trench isolation structure

A method of forming a via. A stacked structure has a barrier layer and a metal line is formed over a substrate. Spacers capable of serving as a barrier are formed over tapering sidewalls of the stacked structure before vias and plugs are formed.

Method of forming via

A method of manufacturing the floating gate of a stacked-gate type of nonvolatile memory unit. A gate oxide layer and a polysilicon layer are sequentially formed over a substrate. The polysilicon layer is etched to form a floating gate above the gate oxide layer. During the polysilicon etching operation, a polymeric material is also deposited on the sidewalls of the floating gate and over the exposed gate oxide. An isotropic chemical dry etching of the floating gate is carried out so that its bottom section is slightly wider than its top section. Finally, a thermal oxidation operation is carried out to form an oxide layer over the floating gate.

Method of manufacturing floating gate of stacked-gate nonvolatile memory unit

A method of reducing a chemical mechanical polishing (CMP) dishing effect. A plurality of trenches are formed in the substrate, while a first insulating layer, such as silicon oxide layer is formed on the substrate to fill those trenches. A chemical reaction, such as nitridation reaction, is performed on the surface of the insulating layer to form a second insulating layer, which is harder than the first insulating layer. CMP is then performed.

Method of reducing CMP dishing effect

A method for forming a T-shaped contact plug is disclosed. A first insulating layer is formed atop of a substrate. A second insulating layer is then formed atop of the first insulating layer. The first and second insulating layers are patterned and etched to form a contact opening to the substrate. A portion of the second insulating layer surrounding the contact opening is removed. Next, a barrier metal layer is formed along the walls of the contact opening and atop the second insulating layer. Then a conducting layer is formed into the contact opening and atop the barrier metal layer. Finally, a portion of the first conducting layer and barrier metal layer atop the second insulating layer is removed. This leaves a plug formed of the remaining portion of the conducting layer.

Method for forming a T-shaped plug having increased contact area

A method of forming hemispherical grain (HSG) silicon is disclosed. The method comprises the steps of: forming a doped amorphous silicon layer on a substrate; seeding and annealing the amorphous silicon layer until HSG silicon is formed; enlarging the HSG silicon grains during the annealing stage; and performing a chemical dry etch on the HSG silicon to remove an undoped silicon layer from the surface of the HSG silicon.

Method for reducing capacitance depletion during hemispherical grain

A method of forming trench type DRAM capacitor. An insulation layer is formed on a substrate with a trench exposing a conductive region of the substrate. A first conductive layer is formed and conformal to a surface profile of the substrate. A photoresist layer is formed over the first conductive layer to fill the trench. A three-stage of etching process is carried out. A first stage of etching step is carried out to remove a portion of the photoresist layer, thereby exposing the first conductive layer. A second stage step is carried out to remove the first conductive layer by performing an isotropic dry etching step. The first conductive layer is slightly over-etched so that a portion of the first conductive layer inside the trench is also removed. Therefore, the first conductive layer inside the trench will be at a distance lower than a top surface of the insulation layer. A third stage of etching operation is carried out to remove the remaining photoresist layer so that the remaining first conductive layer inside the trench is exposed. A dielectric layer and a second conductive layer are sequentially formed over the first conductive layer.

Method of manufacturing DRAM capacitor

A method of fabricating a landing pad. A gate electrode is formed on a substrate. The gate electrode has a top surface covered by a cap layer and a sidewall covered by a spacer. A polysilicon layer is formed to cover the gate. Using an oxygen based etchant to performed an isotropic chemical dry etching on the polysilicon layer, the polysilicon layer is planarized until a part of the spacer is exposed. The polysilicon layer is patterned to form a landing pad in contact with the substrate.

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Taipei, Taiwan

Chingfu Lin