United Microelectronics Corp.

Ching-Yun Chang

Kuo-Chih Lai

Nien-Ting Ho

Yen-Chen Chen

Shih-Min Chou

Yang-Ju Lu

Chi-Mao Hsu

Yun-Tzu Chang

Wei-Ming Hsiao

Hsiang-Chieh Yen

Kuan-Chun Lin

Chia-Chang Hsu

Min-Chuan Tsai

Wei-Ning Chen

Yun Tzu Chang

Fang-Yi Liu

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

Method for fabricating semiconductor device

Semiconductor device and method for fabricating the same

A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

Method for modulating work function of semiconductor device having metal gate structure by gas treatment

A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.

Semiconductor structure and method for manufacturing the same

A semiconductor process of forming metal gates with different threshold voltages includes the following steps. A substrate having a first area and a second area is provided. A dielectric layer and a first work function layer are sequentially formed on the substrate of the first area and the second area. A second work function layer is directly formed on the first work function layer of the first area. A third work function layer is directly formed on the first work function layer of the second area, where the third work function layer is different from the second work function layer. The present invention also provides a semiconductor structure formed by said semiconductor process.

Semiconductor process of forming metal gates with different threshold voltages and semiconductor structure thereof

The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in the method comprises the following steps. (S) providing a substrate having a metal gate structure on a side of the substrate, (S) forming a titanium nitride (TiN) layer on the side of the substrate, and (S) performing a gate annealing to tune work function of the metal gate structure.

Method for tuning metal gate work function before contact formation in fin-shaped field effect transistor manufacturing process

A metal gate forming process includes the following steps. A first metal layer is formed on a substrate by at least a first step followed by a second step, wherein the processing power of the second step is higher than the processing power of the first step.

Metal gate forming process

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Yunlin County, Taiwan

Ching-Yun Chang