Texas Instruments Corporation

Diodes Inc.

Diodes Incorported

Ching-Yuh Tsay

Haydar Bilhan

Gary Lee

Eric G Soenen

Feng Ying

Irfan Azam Chaudhry

Mounir Fares

Yong Han

Alexander Bugeja

M C Ramesh

Chuan Hung Chi

Hugh Pryor McAdams

Wah Kit Loh

Erhan Ozalevli

Ramesh Chandrasekaran

Luthuli E Dake

Ian Lloyd Bower

Richard E Downing

Wen-Chia Yang

Arash Loloee

Jia Li

Craig Lance Dalley

Gregory Romas

Khagendra Thapa

Xucheng Wang

Ying-Tang Cho

George Paul Eaves

Richard Robinson

A sensor device comprises a sensor element for measuring a stimulus and generating a corresponding signal, an ADC for convert the signal to a multi-bit digital signal, a memory unit for storing the digital signal, and a timing unit for switching off the sensor element when the ADC is converting the signal and for switching off the ADC after the digital signal is stored in the memory.

Hall sensor chip with timing control

Some embodiments provide a system that generates a coil switching signal for a brushless DC motor. During operation, the system determines a magnetic field of the brushless DC motor at a first time and a magnetic field of the brushless DC motor at a second time. Then, the coil switching signal is generated based on a relationship between the magnetic field determined at the first time and a first predetermined threshold, and the magnetic field determined at the second time and a second predetermined threshold.

Generating a coil switching signal for a brushless DC motor

Various apparatuses, methods and systems for a voltage regulator are disclosed herein. For example, some embodiments provide an apparatus for regulating a voltage including an N-channel transistor that is connected between an input and an output, an error amplifier that is connected to the output, a capacitor that is connected between the error amplifier and a gate of the N-channel transistor, and a comparator that is connected to a node between the error amplifier and the capacitor. The apparatus also includes a charge pump that is switchably connected to the gate of the N-channel transistor. The apparatus is adapted to connect the charge pump to the gate of the N-channel transistor when a voltage at the node between the error amplifier and the capacitor rises above a threshold voltage.

Voltage regulator with quasi floating gate pass element

A programmable gain amplifier using metal-oxide-semiconductor (MOS) devices to approximate exponential gain characteristic with linear control signals is disclosed. According to one embodiment, the programmable gain amplifier () may include a capacitive switching circuit (), a capacitive switching circuit (), and an operational amplifier (). Capacitive switching circuits (and) may receive an analog input voltage through sample switches (and). Capacitive switching circuit () receives an output from operational amplifier () through feedback switch (). The programmable gain amplifier () may include a few additional unit capacitors which can allow larger gain ranges or more steps for a given range without a large increase in chip size.

Method and apparatus for exponential gain variations with a linearly varying input code

An averaging circuit includes: input signal nodes for providing input signals ; a multiplexing circuit coupled to the input signal nodes for switching between the input signals to create a time waveform; a low pass filter coupled to an output of the multiplexing circuit for filtering the time waveform to create an average signal; and an average replication circuit coupled to an output of the low pass filter

Circuit for precise measurement of the average value of the outputs of multiple circuit unit elements

An image processing apparatus for charge coupled device (CCD) and video inputs in a digital camera or for a digital camcorder is disclosed which provides optical black and offset correction for CCD inputs. A sampling circuit, including correlated double sampler (CDS) ( ) and programmable gain amplifier ( ), samples the image input signal and the video input signal. CDS ( ) includes a single-ended amplifier ( ) and a differential amplifier ( ). The single-ended amplifier ( ) functions such that it is only operable during an CCD signal input; otherwise, the single-ended amplifier ( ) is bypassed such that a video signal is only sampled by the differential amplifier ( ). For CCD signals, the single-ended amplifier ( ) samples the reference level of the pixel and holds it during the video interval. The differential amplifier ( ) samples both the output of the single ended amplifier ( ) and the video level of the same pixel. Overall, the CDS ( ) subtracts these levels and converts the difference to a differential output to improve signal to noise performance and dynamic range. An analog-to-digital converter ( ) converts the sampled signal and feeds this digital sample to a digital correction circuit ( ) where optical black level, hot and cold pixels, and line noise are removed.

CMOS analog front end architecture with variable gain for digital cameras and camcorders

A programmable gain amplifier using metal-oxide-semiconductor (MOS) devices to approximate exponential gain characteristic with linear control signals is disclosed. According to one embodiment, the programmable gain amplifier ( ) may include a capacitive switching circuit ( ), a capacitive switching circuit ( ), and an operational amplifier ( ). Capacitive switching circuits ( and ) may receive an analog input voltage through sample switches ( and ). Capacitive switching circuit ( ) receives an output from operational amplifier ( ) through feedback switch ( ). The programmable gain amplifier ( ) may include a few additional unit capacitors which can allow larger gain ranges or more steps for a given range without a large increase in chip size.

A correlated double sampled/programmable gain amplifier (CDS/PGA) is disclosed which is operable to precondition a CCD output analog signal. The CDS/PGA includes an operational amplifier that is configured in a sample hold operation. The single-ended input is first clamped by a switch ( ) to clamp the DC level therein for a given pixel. A switch ( ) then samples the reset level onto a sampling capacitor ( ), and a switch ( ) thereafter samples the video signal onto one plate of a capacitor ( ). The lower plates of the capacitors ( ) and ( ) are then equalized and the other plates thereof connected to the positive and negative inputs of the operational amplifier ( ). An offset is provided by a programmable DAC ( ) to account for the dark current offset. The output scale is adjusted or mapped by limiting the output between a negative and a positive reference input. The sampling capacitors ( ) and ( ) can be varied to vary the gain of the amplifier.

Complete CDS/PGA sample and hold amplifier

A CMOS programmable gain amplifier ( ) is disclosed which provides exponential gain using a single gain element ( ) which may be implemented in either bipolar or CMOS technology. An embodiment of the present invention includes a first and second sampling impedance ( ), a first and second feedback impedance ( ) and a gain element ( ). The gain element ( ) having an inverting input, a non-inverting input and an output. The inverting input connects to the first sampling impedance ( ). The non-inverting input connects to the second sampling impedance ( ). The first feedback impedance ( ) connects between the inverting input and the output. The second feedback impedance ( ) connects between the non-inverting input and the output.

Capacitor-based exponential programmable gain amplifier

A segmented digital-to-analog converter includes: upper segments , and ; a thermometer decoder ; a randomizing circuit coupled between the thermometer decoder and the upper segments , and for randomizing an output of the thermometer decoder ; a divider location selector circuit coupled between the randomizing circuit and the upper segments , and for choosing a selected segment from the upper segments , and ; and lower segments coupled to the selected segment.

Segmented high speed and high resolution digital-to-analog converter

A plurality of substrate bias circuits (,and,) are designed to provide a stable substrate reference potential for a variety of operating modes. Only one of the bias circuits is enabled by a control circuit (,) at any time for any operational mode. An on-demand boost bias circuit (,) is enabled whenever a level detector (,) indicates substrate bias has exceeded a predetermined limit during special operating modes such as burn-in or parallel test.

Low power substrate bias circuit

A mixed-signal processor (MSP) chip with a flexible serial interface which simultaneously accommodates two serial ports on a reduced number of pins. The pin definitions of these serial ports are configured to function well with several different external chips. Any two of these chips, or two of any one of these chips, may be used concurrently by the present MSP. When used with chips that require it, the present MSP chip provides a clock signal to each of these. When used with other chips, the MSP will can receive a clock signal from an external chip, and will then pass this signal through to any chip on the other of the two serial ports.

Innovative dual-channel serial interface circuit scheme

A trimming circuit for a gain stage in a pipeline analog-to-digital converter includes an amplification stage (30) having associated therewith on one input thereof a coupling capacitor (38). In parallel with the coupling capacitor is provided a trimming network. The trimming network includes a series configuration of a coupling capacitor and a plurality of trimming capacitors, which trimming capacitors can be disposed in parallel with each other. Each of the trimming capacitors has associated therewith a switch which allows them to be selectively disposed in series with a coupling capacitor (42) and in parallel with each other. This trimming network is connected in parallel with the sampling capacitor (38). The input to the amplifier is isolated from the trimming network with a buffer (62) which is operable to isolate the impedance of the trimming capacitors from the input and from preceding stages.

Trimming circuitry for pipeline A/D converter

A trimming algorithm for a pipeline A/D converter includes the step of trimming the input sampling capacitor on each of the gain stages for each stage of the pipeline A/D converter. The input thereof is swept from a minimum to a maximum analog voltage and then the integral non-linearity (INL) of the A/D converter determined. The maximum transitions are then examined to determine which transitions are associated with which stage. The transitions for a given stage then constitute the gain error for these stages. The trim values are determined from this gain error and then the trim values incorporated into each of the gain stages.

Growing community of inventors

Plano, TX, United States of America

Ching-Yuh Tsay