Texas Instruments Corporation

Ching-Yu Hung

Jagadeesh Sankaran

Shinri Inamori

Peter Chang

Deependra Talla

Alan Gatherer

Leonardo William Estevez

Dale E Hocevar

Carl E Lemonds, Jr

Wissam A Rabadi

Minhua Zhou

Alan Davis

Youngjun Yoo

Yinong Ding

Tod David Wolf

Yaqi Cheng

Mel Alan Phipps

David E Smith

Ngai-Man Cheung

Ajay Jayaraj

Nara Won

Shraddha Gondkar

Damon Domke

Clay Dunsmore

Jadadeesh Sankaran

James Nagurne

A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

Vector table load instruction with address generation field to access table offset value

Processor with table lookup processing unit

A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory.

Processor with instruction variable data distribution

A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when executed by the processor, is configured to receive source code and translate the source code to a low-level language. The source code is restricted to a subset of a high-level language and the low-level language is a specialized instruction set. Each statement of the subset of the high-level language directly maps to an instruction of the low-level language.

Systems and methods for software instruction translation from a high-level language to a specialized instruction set

A method for processing digital image data is provided that includes compressing a block of the digital image data to generate a compressed block, storing the compressed block in an external memory when a number of bits in the compressed block does not exceed a first compression threshold, and storing the block in the external memory when the number of bits in the compressed block exceeds the first compression threshold.

Reducing memory bandwidth for processing digital image data

Deblock filtering for Microsoft WMV video decoders partitions the computation so that the deblock filtering operations can be performed on horizontal or vertical stripes or in one pass on oversized macroblocks.

Deblocking filters

An extension to current multiple memory bank video processing architecture is presented. A more powerful memory controller is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.

Parallel architecture for matrix transposition

A method for managing image processing data buffers for processes having overlap input data between iterations includes loading a data buffer with an initial input data array and performing an image data array operation on the input data array. The method repeats the following steps for plural iterations including loading the data buffer with new input data forming a new input data array for a next iteration and performing the input data array operation on the new input data array. The overlap data consists of pixels at an end of each scan line. Loading new input data includes loading pixels following the overlap data for each scan line.

Sliding data buffering for image processing

A digital video acquisition system including a plurality of image processors (A;B) is disclosed. A CCD imager () presents video image data on a bus (video_in) in the form of digital video data, arranged in a sequence of frames. A master image processor (A) captures and encodes a first group of frames, and instructs a slave image processor (B) to capture and encode a second group of frames presented by the CCD imager () before the encoding of the first group of frames is completed by the master image processor. The master image processor (A) completes its encoding, and is then available to capture and encode another group of frames in the sequence. Video frames that are encoded by the slave image processor (B) are transferred to the master image processor (A), which sequences and stores the transferred encoded frames and also those frames that it encodes in a memory (A;). The parameters of the encoding operation can be dynamically adjusted, for example in response to the nature of the video sequences being captured.

Video encoding using parallel processors

A video processing apparatus includes a plurality of processing modules, each performing an image processing function, and a central memory interface. The central memory interface accepts read and write memory the said plurality of processing modules and issues burst memory access requests to an external memory by gathering plural memory access requests from the processing modules.

Video processing subsystem architecture

A programmable data reformatter reorders output from an image sensor to yield various formats. The reformatting applies to reduced resolution output from large image sensors as in digital cameras operating in video mode, and converts an irregular video mode output to a standard format, such as Bayer pattern, for image processing.

Reformatter and method

Polyphase filtering, such as resampling for image resizing, on a processor with parallel output units is cast in terms of data access blocks and data coverage charts to increase processor efficiency. Automatic generation of implementations corresponding to input resampling factors by computation cost comparisons.

Resampling methods for digital images

Context-based adapative binary arithmetic coding (CABAC), as used in video standards such as H.264/AVC, with a renormalization of the interval low value plus range that includes partitioning of the bits of the low value to provide output bits plus low value update without bit-level iterations or aggregation of output bits until a full byte can be output.

Video coding with CABAC

A digital image two-step resizing of filtering an entire image followed by selective row and column deletions. The filtering may use a kernel generated as three samples from a continuous kernel.

Digital still camera system and method

A coprocessor ( ) for synthesizing a signal from the sum of sinusoids preferably includes an electronic system ( ) having a host processor ( ) that forwards frame boundary parameters to the coprocessor ( ). Parameter registers ( ) in coprocessor ( ) store synthesis parameters for iteratively deriving amplitude and phase values for each sample point within a data frame. Adders ( ) generate current amplitude from one addition, and current phase value from two additions, with the results stored back into parameter registers ( ). A sine function calculator circuit ( ), which may use a CORDIC technique, receives the current amplitude and phase values, and generates a digital component signal for the current sample point for one of the sinusoids. Digital component signals are accumulated at the sample point in a data sample buffer ( ) and output at an output ( ).

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Plano, TX, United States of America

Ching-Yu Hung