Lsi Logic Corporation

Ching-Yen Ho

Eric C Cheng

Cheng-Liang Ding

Rochit Rajsuman

An application specific integrated circuit having an embedded microprocessor and core including a memory array, self tests at full operational speed utilizing the computational power of the embedded microprocessor for deterministic testing performed by core specific test algorithms implemented in the assembly code of the embedded microprocessor.

Application specific integrated circuit chip and method of testing same

A method of making, including a method of floorplanning, an integrated circuit includes the separation of electrical logic function cells of the integrated circuit into sets or macros of data path cells, each of which evidence a high level of similarity or repetitiveness in the integrated circuit, and into sets of random logic cells, which each are connected to data path cells but which do not meet topological and connectivity criteria for the data path cells. The data path cells are iteratively sorted according to connectivity requirements and are initially placed on a provisional floor plan of the integrated circuit in a cell-space matrix of rows and columns, the rows being of substantially uniform width to accommodate functional modules of the data path cells, and the rows being of variably height to cooperatively define the spaces of the cell-space matrix. The random logic cells are also iteratively sorted according to connectivety requirements of the integrated circuit and are placed over the data path cells as a provisional overlay of the random logic cells, which are then fitted into any open spaces of the cell-space matrix, and are then inserted into either new rows or new columns of the matrix according to a shape-measuring of the overlay of random logic cells.

Similarity-extraction force-oriented floor planner

An integrated circuit layout technique is described which employs an optimization-driven clustering technique to provide improved cell placement. The technique utilizes clustering of cells based upon Rent's rule, with global-optimization-derived inter-cell distances being used to break ties when identical Rent exponents are encountered. A constraint on the number of cells permitted to be in a cluster and a constraint on the maximum Rent exponent which to be considered for merging clusters minimize the 'overgrowth' of clusters and serve to even out cluster size, ideally suiting the technique to conventional partitioning and placement schemes.

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Saratoga, CA, United States of America

Ching-Yen Ho