Novatek Microelectronics Corp.

Ching-Wu Tseng

Alex Tang

Chih-Hsin Hsu

Wei-Lun Shih

A driver circuit is coupled to a control circuit which is configured to control a plurality of pixels. The driver circuit includes a detector circuit and an outputting circuit. The detector circuit is configured to detect whether an error occurs or not. The outputting circuit is configured to output an enable signal to the control circuit. When the error occurs, the enable signal changes from a first level to a second level such that the control circuit stops outputting a plurality of control signals to the plurality of pixels.

Driver circuit and display device

A gate switch apparatus of a-Si LCDs is provided. The gate switch apparatus is suitable for switching a plurality of sub gate lines and disposed in two rim spaces of a display to make a-Si TFT switch with less impedance. According to a switch driving timing, a plurality of sub gate lines are able to share a single gate line, which saves cost and reduces the difficulty in the manufacturing process.

Gate switch apparatus for amorphous silicon LCD

A method for driving an LCD monitor includes providing a common-voltage signal having a level conversion during each frame duration, dividing each frame duration into a first sub-frame duration and a second sub-frame duration according to a position having the level conversion of the common-voltage signal, driving a first set of pixel units during the first sub-frame duration according to a level of the common-voltage signal within the first sub-frame duration, and driving a second set of pixel units during the second sub-frame duration according to a level of the common-voltage signal within the second sub-frame duration.

Method for driving LCD monitor for displaying a plurality of frame data during a plurality of frame durations

A gate driving device comprises a control circuit, a shift register circuit, a level shifter, a buffer block and a current overdrive protection device. The control circuit receives and outputs the logic control signals. The shift register circuit receives the logic control signals and sequentially outputs N horizontal low-voltage pulse signals from the first to Nth horizontal lines. The level shifter receives and transforms the horizontal low-voltage pulse signals into positive/negative high-voltage signals. The buffer block receives the horizontal positive/negative high-voltage signals and buffers the driving of the output level device. The current overdrive protection device receives the logic control signal and the horizontal low-voltage pulse signals. The current overdrive protection device, while being properly triggered, outputs the reset signal to prevent the sudden current spike. Accordingly, the damage of the gate driving device is avoided.

Gate driving device with current overdrive protection and method thereof

A method of layout of a driving chip of an LCD, for reducing a size of the LCD, includes forming a first pin group including a plurality of pins utilized for outputting gate driving signals along a first direction, forming a second pin group including a plurality of pins utilized for outputting gate driving signals along the first direction, forming a first wire group including a plurality of wires each coupled between a pin of the first pin group and a panel of the LCD, and forming a second wire group including a plurality of wires each coupled between a pin of the second pin group and the panel, wherein each wire of the second wire group includes at least a bender formed inside the driving chip.

Layout method and structure for driving chip of an LCD having first and second pin groups only along a horizontal direction of the LCD and first and second wiring groups for the respective pin groups with wires of the second group having a bend inside the driving chip

A latchable voltage level shifter is provided. The latchable voltage level shifter comprises: a voltage level shifter receiving an original input signal and generating a high voltage signal according to a timing sequence of a first phase control signal; and a high voltage flip-flop, coupled to the voltage level shifter, receiving the high voltage signal and a second phase control signal, the high voltage flip-flop latching the high voltage signal according to a timing sequence of the second phase control signal and outputting a high voltage output signal. The latchable voltage level shifter can be used in a source drive circuit so as to reduce the layout area and production cost.

Source drive circuit

A voltage level shifter is provided. The shifter includes an AND gate for generating a synchronizing signal according to a periodic signal and a primitive input signal. The synchronizing signal and a first periodic control signal that are in phase with the periodic control signal are inputted to a transistor device. The transistor device is constructed with an inverter. The voltage level shifter further includes a buffer for generating an output signal and a capacitor for storing a signal. The present invention also provides a switching circuit for preventing the turning on of both PMOS transistor and NMOS transistor simultaneously during a switching status. The present invention can also solve the issue caused by the ratio of the channel width to the channel length, thus the uncertainty of the manufacturing process will not affect the circuit. Therefore, the power consumption, the chip area and the cost are reduced.

Growing community of inventors

Taipei County, Taiwan

Ching-Wu Tseng