Vanguard International Semiconductor Corporation

Ching-Wen Wang

Hung-Wei Chen

Chi-Li Tu

Shi-Hsiang Lu

Shao-Chang Huang

Chih-Hsuan Lin

Li-Fan Chen

Chun-Chih Chen

Karuna Nidhi

Ting-You Lin

Yu-Kai Wang

An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.

Electrostatic discharge protection circuit

A method for fabricating a bonding pad structure includes forming a dielectric layer on a substrate; forming a first metal pattern layer in the dielectric layer. The first metal pattern layer includes a first body portion having a plurality of first openings in a central region of the first body portion and a plurality of second openings arranged along a peripheral region of the first body portion and surrounding the plurality of first openings; and a plurality of first island portions correspondingly disposed in the plurality of second openings and spaced apart from the first body portion. The method further includes forming a plurality of first interconnect structures in the dielectric layer and corresponding to the plurality of first island portions; and forming a bonding pad on the dielectric layer and directly above the first metal pattern layer.

Bonding pad structure having island portions and method for manufacturing the same

The invention provides a semiconductor device layout structure disposed in an active region. The semiconductor device layout structure includes a first well region having a first conduction type. A second well region having a second conduction type opposite the first conduction type is disposed adjacent to and enclosing the first well region. A first doped region having the second conduction type is disposed within the first well region. A second doped region having the second conduction type is disposed within the first well region. The second doped region is separated from and surrounds the first doped region. A third doped region having the second conduction type is disposed within the second well region.

Semiconductor device layout structure

A bonding pad structure is provided. The structure includes a dielectric layer on a substrate. A bonding pad is disposed on the dielectric layer and a first metal pattern layer is embedded in the dielectric layer and directly below the bonding pad. The first metal pattern layer includes a first body portion and first island portions. The first body portion has first openings in a central region of the first body portion and second openings arranged along a peripheral region of the first body portion and surrounding the first openings. The first island portions are correspondingly disposed in the second openings and spaced apart from the first body portion. First interconnect structures are disposed in the dielectric layer and correspond to the first island portions, such that the bonding pad is electrically connected to the first island portions.

Growing community of inventors

Hemei, Taiwan

Ching-Wen Wang