Sunplus Technology Co., Ltd.

Via Technologies, Inc.

Ching-Wen Ma

Yung-Chi Yang

Shih-Hsien Liu

Kuo-Ming Wang

Zheng-Xiong Chen

Jia-Ping Chen

A circuit for generating a tracking error signal is provided. The circuit includes a digitizing circuit, a short signal removing circuit and phase comparator. The digitizing circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.

Circuit for generating tracking error signal

A circuit for generating a tracking error signal is provided. The circuit includes a digitized circuit, a short signal removing circuit and phase comparator. The digitized circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.

An automatic gain control system with hysteresis switching includes an error calculator for calculating the difference between a first estimation signal and a take over point (TOP) value to produce an error signal. A hysteresis comparator compares the first estimation signal and the TOP value to produce a control signal. A first gain control loop generates a first gain control signal based on the control signal to control a gain of a first variable gain amplifier. A second gain control loop generates a second gain control signal based on the control signal to control a gain of a second variable gain amplifier. As the first estimation signal leaves a hysteresis region of the hysteresis comparator, the first gain control signal is monotonically decreasing and the first gain control signal is monotonically increasing. As a result, the total gain is stable.

Automatic gain control loop with hysteresis switching

A control system determines read performance of an optical storage device according to lock performance of a re-timing signal. The control system includes a filtering and re-timing unit for receiving a radio frequency (RF) signal and outputting the re-timing signal and an un-corrected output signal, an error correction unit for receiving the un-corrected output signal and correcting an error bit according to a Reed-Solomon algorithm to generate a corrected output signal, a lock performance detector for receiving the re-timing signal and detecting the lock performance of the re-timing signal and then outputting a lock performance index, and a servo control loop for receiving the RF signal and the lock performance index and thus generating a servo control signal. When the lock performance index does not reach a threshold value, the servo control loop loads other control parameters to improve the read performance of the optical storage device.

Control system for an optical storage device

An ECC decoder for correcting a coded signal received, which includes a syndrome calculation and errata evaluation device to receive a code word of the coded signal for performing a syndrome calculation to thereby output a syndrome polynomial, and to receive an erasure and errata evaluator polynomial and an errata position for performing an errata evaluation to thereby output an errata and erasure value and correct the coded signal; a key equation solving device to receive the syndrome for generating an erasure and errata locator polynomial and the erasure and errata evaluator polynomial; and an errata position search device to receive the erasure and errata locator polynomial for searching and outputting the errata position. Evaluating the errata and erasure value and calculating the syndrome are performed in pipeline, thereby sharing the hardware and relatively reducing the hardware cost.

Error correction code decoder

A timing recovery circuit and related method is disclosed. The timing recovery circuit encompasses a converter, an interpolator, a phase error detector, an adjustment circuit, and a calculation circuit. The converter samples an input signal to generate an intermediate signal carrying samples of the input signal, while the interpolator inserts an interpolating sample into the intermediate signal in response to a control value to generate an output signal. The phase error detector outputs a phase error of the output signal. The adjustment circuit updates an over-sampling ratio according to a pair of first and second thresholds, and a counting value adjusted in response to the phase error and a median reference value. Finally, the calculation circuit derives the control value from the updated over-sampling ratio, and transferring the control value to the interpolator.

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Nantou, Taiwan

Ching-Wen Ma