Novatek Microelectronics Corp.

Ching-Wen Lai

Hsi-Chi Ho

Sheng-Yuan Chu

A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N&#xd7;M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N&#xd7;M arbiters, generates N&#xd7;M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N&#xd7;M arbiters to sequentially control the N&#xd7;M arbiters.

Memory architecture for display device and control method thereof

When receiving request commands from different hosts, a data system generates corresponding phase control signals and access signals based on the formats of each request command. Based on the phase control signals, timing signals corresponding to respect request commands and including a plurality of enabling time slots are generated in a way that only one timing signal includes an enabling time slot at a certain point of time. Next, an access control signal is outputted to a storage device during the enabling time slot of a corresponding timing signal. Therefore, the storage device only needs to respond to one request command at a certain point of time, and multiple data access can be effectively controlled in the data system.

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Hsinchu, Taiwan

Ching-Wen Lai