United Microelectronics Corp.

Ching-Wen Hung

Chih-Sen Huang

Jia-Rong Wu

Yi-Wei Chen

Yi-Hui Lee

Po-Chao Tsao

Ying-Cheng Liu

Chun-Hsien Lin

Chia-Lin Lu

Ching-Ling Lin

Feng-Yi Chang

Chieh-Te Chen

Chun-Lung Chen

Tsung-Hung Chang

Shih-Hung Tsai

Shih-Fang Tzou

Kun-Yuan Liao

Ya-Sheng Feng

Yi-Kuan Wu

En-Chiuan Liou

Yu-Ping Wang

Chia-Wei Huang

Wei-Hao Huang

Chien-Ting Lin

Yung-Feng Cheng

Shu-Ru Wang

Ling-Chun Chou

I-Chang Wang

Po-Kuang Hsieh

Li-Wei Feng

Chun-Hsien Huang

Chih-Kai Hsu

Jyh-Shyang Jenq

Yu-Tse Kuo

Ming-Jui Chen

Chao-Hung Lin

Kun-Ju Li

Yi-Ching Wu

Li-Ping Huang

Tan-Ya Yin

Hsiang-Hung Peng

Wei-Cyuan Lo

Yu-Cheng Tung

Chien-Hung Zordius Chen

Chih-Wei Yang

Yu-Tsung Lai

Hsin-Fu Huang

Rai-Min Huang

Chia-Chang Hsu

Shih-Fang Hong

Hsuan-Hsu Chen

Wei-Chuan Tsai

Chia Chang Hsu

Yen-Tsai Yi

Kuo-Liang Yeh

Ching-Pin Hsu

Yu-Lin Wang

Jun-Jie Wang

Shu-Min Huang

Ying-Ren Chen

Chien-Ying Sun

Chorng-Lih Young

Chien-Tung Yue

Jinn-Horng Lai

Chun-Li Lin

Peng-Hsiu Chen

Su-Ming Hsieh

Meng-Chi Chiang

Yen-Chih Lin

The invention provides a layout pattern of a semiconductor varactor, which comprises a plurality of varactor units arranged on a substrate, wherein each varactor unit comprises a plurality of fin structures arranged in parallel with each other, a plurality of gate structures arranged in parallel with each other, located on the substrate and spanning the fin structures, and a gate metal layer electrically connected with the plurality of gate structures.

Layout pattern of semiconductor varactor and forming method thereof

A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; and removing the sacrificial layer.

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Nanowire transistor and method for fabricating the same

A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.

Semiconductor device structure and manufacturing method thereof

A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

Static random access memory and method for fabricating the same

The present invention provides a method of generating dummy patterns and calibration kits, including steps of generating devices-under-test (DUTs) using a point of said chip window layer as reference point in a unit cell, generating calibration kits corresponding to the DUTs using the point as reference point in corresponding unit cells, generating DUT dummy patterns for each DUTs individually in the unit cell, copying the DUT dummy patterns in the unit cell to the corresponding calibration kits in the corresponding unit cells using the point as reference point, and merging all of the unit cell and corresponding unit cells into a final chip layout.

Method of generating dummy patterns for device-under-test and calibration kits

Growing community of inventors

Tainan, Taiwan

Ching-Wen Hung