Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Industrial Technology Research Institute

Au Optronics Corporation

Adeia Semiconductor Bonding Technologies Inc.

Chunghwa Picture Tubes, Ltd.

Hannstar Display Corporation

Chi Mei Optoelectronics Corporation

Toppoly Optoelectronics Corporation

TSMC Solid State Lighting Ltd.

Quanta Display Inc.

Taiwan Tft Lcd Association

Epistar Corporation

Ching-Wen Hsiao

Chen-Shien Chen

Chih-Hua Chen

Ming-Da Cheng

I-Hsuan Peng

Yen-Chang Hu

Wei Sen Chang

Tzu-Hung Lin

Chen-Cheng Kuo

Mirng-Ji Lii

Shou-Cheng Hu

Chen-Hua Douglas Yu

Chih-Wei Lin

Kuo-Ching Hsu

Shou-Lung Chen

Jyh-Rong Lin

Tin-Hao Kuo

Yu-Hua Chen

Shan-Pu Yu

Jeng-Dar Ko

Tsung-Ding Wang

Yao-Chun Chuang

Hon-Lin Huang

Kai-Ming Ching

Hong-Seng Shue

Hsien-Wei Chen

Chung-Shi Liu

Shin-Puu Jeng

Der-Chyang Yeh

Li-Hsien Huang

Ming Hung Tseng

Kuo Lung Pan

Chih-Ming Tzeng

Po-Hao Tsai

Chien Ling Hwang

Yu-Chih Huang

Sheng-Yu Wu

Tsung-Hsien Chiang

Chyi Shyuan Chern

Wei-Che Huang

Hsin-Hsien Wu

Nai-Wei Liu

Kuang-Huan Hsu

Chiang-Jui Chu

Hao-Chun Liu

Hao Chun Liu

Tao-Sheng Chang

Young-Hwa Wu

Chun-Hung Chen

Chun-Lin Louis Chang

Chita Chuang

Chang-Jung Hsueh

Hao-Juin Liu

Ting-Li Yang

Ching-Hui Chen

Hsu-Hsien Chen

Shang-Yun Tu

Ru-Ying Huang

Fang-Jun Leu

Yu-Tse Su

Bang-Hao Wu

Wan-Yu Chiang

Jian-Shu Wu

Hsin-Chun Chiang

Ming-Hong Tseng

Wei-Han Chiang

Ching-Ho Cheng

Cheng-Nan Lin

Sut-I Lo

Hui-Mei Wu

Chien-Wei Chieh

Yu-Ming Chen

Wen-Chih Chiou

Alexander Kalnitsky

Shang-Yun Hou

Jiun Yi Wu

Wei-Hung Lin

Han-Ping Pu

Yen-Liang Lin

Chien-Hsiun Lee

Chih-Hsien Lin

Chung-Wen Wu

Chang-Chia Huang

Ta-Sung Lee

Pei-Chun Tsai

Tung-Hsien Hsieh

Wen-Wei Shen

Bai-Yao Lou

Sheng-Ming Chang

Yung-Chang Chen

Tzy-Kuang Lee

Chi-Chin Lien

Hsiao-Wen Chung

Yuan-Yao Chang

Dean Wang

Shan-Yu Huang

Fu-Wen Liu

Ding-Chung Lu

Meng-Hsiu Hsieh

Wei-hung Lin

A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

Semiconductor device with discrete blocks

A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Semiconductor device, semiconductor package, and methods of manufacturing the same

A semiconductor package includes a conductive pillar and a solder. The conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. The solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.

Semiconductor packages having conductive pillars with inclined surfaces

A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.

Bump integration with redistribution layer

An inductor includes a core and a conductive spiral wound around the core. The core includes a buffer layer, an etch stop layer, and a core material layer sequentially stacked. The core material layer includes a ferromagnetic material. A total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer. The vertical projection of the core material layer falls entirely on the etch stop layer. The etch stop layer horizontally protrudes with respect to the core material layer.

Semiconductor device with inductor windings around a core above an encapsulated die

A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

Passivation layer and planarization layer and method of forming the same

An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the interconnect-level dielectric material layers, at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers, a bonding-level dielectric layer located on the at least one dielectric capping layer, metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, and an edge seal ring structure vertically extending from a first horizontal plane including bonding surfaces of the package-side bump structures to a second horizontal plane including distal planar surfaces of the metallic pad structures. The edge seal ring structure may include a vertical stack of metallic ring structures that are free of aluminum and laterally surround the package-side bump structures and the redistribution interconnect structures.

Interposer including a copper edge seal ring structure and methods of forming the same

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.

Bonding structures in semiconductor packaged device and method of forming same

A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

Package structures and methods for forming the same

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.

Chip structure with conductive via structure and method for forming the same

A semiconductor package includes a first device, a second device and a solder region. The first device includes a first conductive pillar, wherein the first conductive pillar has a first sidewall, a second sidewall opposite to the first sidewall, a first surface and a second surface physically connected to the first surface, the first surface and the second surface are disposed between the first sidewall and the second sidewall, and an included angle is formed between the first surface and the second surface. The solder region is disposed between the first conductive pillar and the second device to bond the first device and the second device.

An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.

Organic interposer including a dual-layer inductor structure and methods of forming the same

A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

Alignment mark design for packages

Growing community of inventors

Hsinchu, Taiwan

Ching-Wen Hsiao