National Chung Cheng University

Other

Ching-Wei Yeh

Jinn-Shyan Wang

Tay-Jyi Lin

Ching-Rong Chang

Che Chia Pai

Zhi-Xin Lin

Che-Chia Pai

Yuan-Hsiang Miao

Hsi Che Wang

Shau-Chian Tang

Ching-Hau Sung

Ying-Jie Xu

A device and a method for clarifying dysarthria voices is disclosed. Firstly, a dysarthria voice signal is received and framed to generate dysarthria frames. Then, the dysarthria frames are received to retrieve dysarthria features. Finally, the dysarthria features are received. Without receiving phases corresponding to the dysarthria features, the dysarthria features are converted into an intelligent voice signal based on an intelligent voice conversion model. The intelligent voice conversion model is not trained by the dynamic time warping (DTW). The present invention avoids the phase distortion of the voice signal and provides more natural and clarified voices with low noise.

Device and method for clarifying dysarthria voices

A system for improving dysarthria speech intelligibility and method thereof, are provided. In the system, user only needs to provides a set of paired corpus including a reference corpus and a patient corpus, and a speech disordering module can automatically generate a new corpus completely synchronous with the reference corpus, and the new corpus can be used as a training corpus for training a dysarthria voice conversion model. The present invention does not need to use a conventional corpus alignment technology or a manual manner to perform pre-processing on the training corpus, so that manpower cost and time cost can be reduced, and synchronization of the training corpus can be ensured, thereby improving both training and conversion qualities of the voice conversion model.

System for improving dysarthria speech intelligibility and method thereof

A video device for realtime pedaling frequency estimation is mounted on a bike and comprises an image capture unit capturing continuous dynamic images of an upper body of a biker; an image recognition unit recognizing images of symmetric regions of the biker and images of swings of the symmetric regions from the continuous dynamic images; a microprocessor calculating a frequency of periodical swings of the biker from the images of the symmetric regions and the images of the swings of the symmetric regions, and then obtaining a pedaling frequency; and a display device presenting the pedaling frequency, wherein a widely-used intelligent handheld device replaces the sensors, display device, and complicated circuits of the conventional cyclometer, and wherein a novel image recognition technology is used to measure the pedaling frequency with a considerable accuracy in a lower cost and a convenient way.

Video device for realtime pedaling frequency estimation

A data processing method for a context formation module and an arithmetic encoder in an embedded block coding with optimized truncation (EBCOT) module includes inputting column-based data into the context formation module, controlling the context formation module with a finite state so that the context formation module has a constant valid output in each clock cycle, separating the calculation and the normalization operation of registers into different pipeline stages of the arithmetic encoder, and interleaving inputs so that two different data are inputted into the arithmetic encoder in one clock cycle difference.

Data processing method in embedded block coding with optimized truncation module

An apparatus for processing an image with a discrete wavelet transform is provided. For one-dimensional circuit, the method changes conventional image data processing flow and uses common product of sequential calculations with respect to the time axis. The calculations for input data are not repeated so that components of the hardware architecture are minimized. For two-dimensional circuit, the method uses an external data scanning method to eliminate an external memory, transposing buffer, from a transforming circuit.

Method for processing digital image with discrete wavelet transform and apparatus for the same

A low power dynamic logic circuit. By shifting a discharge NMOS transistor of a conventional dynamic logic circuit between an output terminal and a logic block, plus an additional charge and discharge control, the operation speed and power consumption of a dynamic circuit can be effectively improved. Using the charge redistribution to speed up the circuit operation and to reduce the body effect that affects the operation speed, the speed of the novel dynamic logic circuit is enhanced. By transferring the lump capacitor of the charge/discharge, the dynamic power can be effectively reduced. The lower power dynamic logic circuit can be used independently or combined with a conventionally dynamic logic circuit.

Low power dynamic logic circuit

An assembling method for a low-power programmable logic array circuit. The assembling method is capable of reducing delays and unnecessary power consumption. According to the low potential power loss when the dynamic gates in the AND-plane and the OR-plane output a low potential, the high potential power loss when the dynamic gates in the AND-plane and the OR-plane output a high potential and the probability of the dynamic gates outputting a high potential, a selection between new dynamic logic circuit and conventional dynamic circuit is carried out. The conventional dynamic circuit in the AND-plane refers to a conventional dynamic circuit whereas the conventional dynamic circuit in the OR-plane refers to a conventional footless dynamic circuit

Growing community of inventors

Chia-Yi, Taiwan

Ching-Wei Yeh