Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

TSMC Nanjing Company, Limited

TSMC China Company, Limiied

Ching-Wei Wu

He-Zhou Wan

Hung-Jen Liao

Jui-Che Tsai

Kuang Ting Chen

Cheng Hung Lee

Xiu-Li Yang

XiuLi Yang

Kuan Cheng

Chia-Cheng Chen

Hidehiro Fujiwara

Hau-Tai Shieh

Yi-Tzu Chen

Ming-Hung Chang

Pankaj Aggarwal

Ming-En Bu

Cheng-Hung Lee

Atul Katoch

Kao-Cheng Lin

Saman M I Adham

Hao-I Yang

Donald George Mikan, Jr

Tsung-Yung Chang

Ming-Chien Tsai

Uppu Sharath Chandra

Luping Kong

Chia-En Huang

Fu-An Wu

Jaymeen Bharatkumar Aseem

Pei-Le Li

Chung-Hsing Wang

Feng-Ming Chang

Hong-Chen Cheng

Mu-Jen Huang

Jung-Hsuan Chen

Chun-Hao Chang

Tzu-Kuei Lin

Chien Chi Tien

Weiyang Jiang

Wei-Shuo Kao

Wenchao Hao

Yen-Huei Chen

Ping-Wei Wang

Chung-Cheng Chou

Shao-Yu Chou

Chia-en Huang

Chien-Yu Huang

Wei-Yang Jiang

Lee Cheng Hung

Shu-Hsuan Lin

Ming-hung Chang

Li-Chen Chen

Ruei-Chin Luo

Jun Xie

Peijiun Lin

Zhi-Min Zhu

Jun-Cheng Liu

Harn-Bor Yang

Hung-Je Liao

Bin Sheng

An integrated circuit includes integrated circuit includes a memory bank, a first group of word lines, a second group of word lines, an access circuit, a converter circuit and a decoder circuit. The first group of word lines is coupled to the memory bank. The second group of word lines is coupled to the memory bank, and arranged in order with the first group of word lines. The access circuit is configured to read the memory bank. The converter circuit is configured to control the access circuit at least based on a first control signal. The decoder circuit is configured to generate the first control signal at least according to a first bit and a second bit of an address signal. The first bit and the second bit indicates one group of the first group of word lines and the second group of word lines.

Integrated circuit with asymmetric arrangements of memory arrays

An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

Scan synchronous-write-through testing architectures for a memory device

A memory device is provided and includes a memory array, first to second latch circuits and a gating circuit. Read and write operations are triggered by first and second edges of an internal clock signal respectively. The first latch circuit generates a first output signal in response to an input signal and a first latch clock signal, a first edge of the first latch clock signal generated based on the first edge of the internal clock signal. The second latch circuit generates a second output signal in response to the first output signal and a second latch clock signal, a first edge of the second latch clock signal being between first and second edges of the first latch clock signal. The gating circuit generates, in response to the second output signal and a gating clock generated, a third output signal to the memory array.

Memory structure with optimized latch clock design

A memory circuit includes a control circuit coupled to the word line driver circuit. The control circuit is configured to delay a leading or falling edge of a word line signal in response to at least a first clock signal. The control circuit includes a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to adjust a delay between the second and third clock signal in response to the second clock signal and an enable signal. The third clock signal is a delayed version of the second clock signal. An amount of the delay between the second and third clock signal is based on a voltage difference between a first supply voltage having a first swing, and a second supply voltage having a second swing.

Memory circuit and method of operating same

A memory device is provided, including at least one bit cell, a pair of transistors, and a voltage generation circuit. The voltage generation circuit is coupled to the negative voltage line and is configured to pull down a voltage of at least one of the pair of data lines to a negative voltage level through the negative voltage line. The voltage generation circuit includes a first capacitive unit, a second capacitive unit, and a switch circuit. The first capacitive unit includes a first capacitor. The second capacitive unit includes a second capacitor. The switch circuit is configured to connect the first capacitor, the second capacitor, or the combination thereof to the negative voltage line in response to a first kick signal and a second kick signal that are different from each other.

Memory device and operating method thereof

A circuit includes an array including a plurality of memory cells; a driver operatively coupled to the array and configured to provide an access signal controlling an access to one or more of the plurality of memory cells; and a timing controller operatively coupled to the driver. The timing controller is configured to: receive a control signal; and in response to the control signal transitioning from a first logic state to a second logic state, adjust a pulse width of the access signal within a single clock cycle containing a first phase and a second phase, wherein the first phase includes reading a first data bit stored in a first one of the one or more memory cells and the second phase includes writing a second data bit into the first memory cell.

Memory circuits with dynamically adjustable pulse widths and methods for operating the same

A memory device is provided, including an array of bit cells and a set of tracking cells. The set of tracking cells is arranged adjacent to the array of bit cells along a first direction. The set of tracking cells includes a set of first tracking cells configured to perform a read tracking operation and a set of second tracking cells configured to perform a write tracking operation and arranged adjacent to the set of first tracking cells along a second direction. First tracking cells in the set of first tracking cells are coupled in series with each other and arranged along the second direction, and second tracking cells in the set of second tracking cells are coupled in series with each other and arranged along the second direction.

Memory device and method for operating the same

Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

Sub-word line driver placement for memory device

A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.

Circuit and method of operating the same

A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.

Latch circuit and memory device

A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Memory circuit and method of operating the same

A circuit includes a series of a first latch circuit, selection circuit, second latch circuit, and pre-decoder. A control circuit, based on a clock signal, outputs control signals to the selection circuit and first and second latch circuits, and, to the pre-decoder, a pulse signal including a first pulse during a first portion of a clock period in response to a read enable signal having a first logical state, and a second pulse during a second portion of the clock period in response to a write enable signal having the first logical state. Based on the control signals, the selection circuit and first and second latch circuits output read and write addresses to the pre-decoder during the respective first and second clock period portions, and the pre-decoder outputs a partially decoded address in response to each of the read address and first pulse, and the write address and second pulse.

Shared decoder circuit and method

A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.

Memory device

A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. The latch clock generator includes a first inverter configured to generate an inverted signal of the first enable signal, and a NAND gate coupled to the first inverter to receive the inverted signal of the first enable signal. The NAND gate is configured to generate the latched clock signal based on the clock signal and the inverted signal of the first enable signal.

Latch circuit, memory device and method

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Caotun Town, Taiwan

Ching-Wei Wu