Taiwan Semiconductor Manufacturing Comp. Ltd.

National Central University

Personal Genomics, Inc.

Other

Macronix International Co., Ltd.

Scinopharm Taiwan, Ltd.

Personal Genomics Taiwan, Inc.

Ching-Wei Tsai

Chih-Hao Wang

Kuan-Lun Cheng

Kuo-Cheng Ching

Ying-Keung Leung

Kuo-Cheng Chiang

Yu-Xuan Huang

Cheng-Ting Chung

Shang-Wen Chang

Pei-Yu Wang

Shi Ning Ju

Hou-Yu Chen

Wai-Yi Lien

Yi-Hsun Chiu

Sai-Hooi Yeong

Chi-Wen Liu

Carlos H Diaz

Kai-Chieh Yang

Yi-Bo Liao

Min Cao

Cheng-Chi Chuang

Chih-Liang Chen

Chi-Hsing Hsu

Kuan-lun Cheng

Jhon Jhy Liaw

Huan-Chieh Su

Shi-Ning Ju

Jiann-Tyng Tzeng

Zhiqiang Wu

Chun-Yuan Chen

Chung-Cheng Wu

Jiun-Jia Huang

Wen-Hsing Hsieh

Wei-Hao Wu

Yi-Hsiung Lin

Chih-Yu Lai

Wei Ju Lee

Chia-Hao Chang

Hui-Zhong Zhuang

Zhi-Chang Lin

Pang-Yen Tsai

Kuan-Ting Pan

Chi-Yu Lu

Tzer-Min Shen

Jon-Hsu Ho

Ru-Gun Liu

Chih-Ming Lai

Yeur-Luen Tu

Jam-Wem Lee

Charles Chew-Yuen Young

Chung-Hui Chen

Yasutoshi Okuno

Mao-Lin Huang

Jia-Ni Yu

Kuo-Ji Chen

Chung-Wei Hsu

Yu-Hung Cheng

Lung-Kun Chu

Pei-Hsun Wang

Wei-An Lai

Chih-Chao Chou

Jui-Chien Huang

Wei-Li Chen

Guan-Lin Chen

Lei-Chun Chou

Li-Chun Tien

Wei-Cheng Lin

Yih Wang

Bo-Feng Young

Jean-Pierre Colinge

Lin-Yu Huang

Li-Zhen Yu

Jia-Chuan You

Chih-Yu Chang

Jung-Hung Chang

Tien-Wei Chiang

Chung-Wei Wu

Lo-Heng Chang

Chun-Fu Cheng

Li-Shyue Lai

Wen-Ting Lan

Chao-Chi Pan

Teng-Chun Tsai

Huicheng Chang

Chenming Hu

Chia-En Huang

Shih-Wei Peng

Chun-Hsiung Lin

Li-Ting Wang

Cheng-Tung Lin

Wei-Jung Lin

Te-Hsin Chiu

Guo-Huei Wu

Min-Hwa Chi

Kuo-Yin Lin

Chung-Fan Chiou

Chia-en Huang

Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

Self-aligned metal gate for multigate device

A semiconductor device includes a substrate. The semiconductor device further includes a first gate structure on a first side of the substrate. The semiconductor device further includes a second gate structure on a second side of the substrate, wherein the first side is opposite the second side. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

Method of making amphi-FET structure and method of designing

The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

High-voltage nano-sheet transistor

A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.

Air spacer and capping structures in semiconductor devices

Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first channel structure, a first gate dielectric layer surrounding the first channel structure, and a first metal gate surrounding first gate dielectric layer. The first metal gate includes a first metal layer in direct contact with the first gate dielectric layer and a first metal cap in direct contact with the first gate dielectric layer, wherein the first metal cap is in direct contact with the first metal layer.

Semiconductor device and method of forming thereof

Methods of forming dual-side super power rails in semiconductor devices, semiconductor devices including the same, and methods of testing the semiconductor devices are disclosed. In an embodiment, a device includes a transistor structure; a front-side interconnect structure on a front side of the transistor structure; and a back-side interconnect structure on a back side of the transistor structure. The front-side interconnect structure includes a front-side power delivery network (PDN) and a front-side input/output (I/O) pin. The back-side interconnect structure includes a back-side PDN.

Dual-side power rail design and method of making same

A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.

Method for metal gate cut and structure thereof

A semiconductor device according to the present disclosure includes a first plurality of gate-all-around (GAA) devices in a first device area and a second plurality of GAA devices in a second device area. Each of the first plurality of GAA devices includes a first vertical stack of channel members extending along a first direction, and a first gate structure over and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes a second vertical stack of channel members extending along a second direction, and a second gate structure over and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length and each of the second plurality of GAA devices includes a second channel length smaller than the first channel length.

Low leakage device

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Integrated circuit structure and method with hybrid orientation for FinFET

The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

Metal oxide interlayer structure for NFET and PFET

A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

Negative capacitance transistor with a diffusion blocking layer

A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Method of making semiconductor device having self-aligned interconnect structure

A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.

Semiconductor device structure and method for forming the same

Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.

Backside power rail for physical failure analysis (PFA)

A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Backside signal interconnection

Growing community of inventors

Hsinchu, Taiwan

Ching-Wei Tsai