Taiwan Semiconductor Manufacturing Comp. Ltd.

National Central University

Personal Genomics, Inc.

Other

Macronix International Co., Ltd.

Scinopharm Taiwan, Ltd.

Personal Genomics Taiwan, Inc.

Ching-Wei Tsai

Chih-Hao Wang

Kuan-Lun Cheng

Kuo-Cheng Ching

Yu-Xuan Huang

Kuo-Cheng Chiang

Ying-Keung Leung

Cheng-Ting Chung

Shang-Wen Chang

Pei-Yu Wang

Hou-Yu Chen

Yi-Hsun Chiu

Shi Ning Ju

Sai-Hooi Yeong

Wai-Yi Lien

Chi-Wen Liu

Carlos H Diaz

Cheng-Chi Chuang

Kai-Chieh Yang

Yi-Bo Liao

Min Cao

Chih-Liang Chen

Chi-Hsing Hsu

Kuan-lun Cheng

Huan-Chieh Su

Jhon Jhy Liaw

Jiann-Tyng Tzeng

Chun-Yuan Chen

Shi-Ning Ju

Chih-Yu Lai

Zhiqiang Wu

Chung-Cheng Wu

Wei Ju Lee

Jiun-Jia Huang

Hui-Zhong Zhuang

Wei-Hao Wu

Wen-Hsing Hsieh

Chi-Yu Lu

Yi-Hsiung Lin

Chia-Hao Chang

Zhi-Chang Lin

Mao-Lin Huang

Kuan-Ting Pan

Pang-Yen Tsai

Jia-Ni Yu

Lung-Kun Chu

Tzer-Min Shen

Jon-Hsu Ho

Ru-Gun Liu

Chih-Ming Lai

Li-Chun Tien

Yeur-Luen Tu

Wei-Cheng Lin

Bo-Feng Young

Li-Zhen Yu

Jam-Wem Lee

Charles Chew-Yuen Young

Chung-Hui Chen

Yasutoshi Okuno

Chung-Wei Hsu

Kuo-Ji Chen

Yu-Hung Cheng

Pei-Hsun Wang

Wei-An Lai

Jui-Chien Huang

Chih-Chao Chou

Guan-Lin Chen

Wei-Li Chen

Lei-Chun Chou

Yih Wang

Shih-Wei Peng

Lin-Yu Huang

Jean-Pierre Colinge

Jia-Chuan You

Chih-Yu Chang

Jung-Hung Chang

Tien-Wei Chiang

Lo-Heng Chang

Chung-Wei Wu

Chun-Fu Cheng

Chia-en Huang

Li-Shyue Lai

Wen-Ting Lan

Teng-Chun Tsai

Huicheng Chang

Chia-En Huang

Chenming Hu

Chun-Hsiung Lin

Li-Ting Wang

Wei-Jung Lin

Cheng-Tung Lin

Te-Hsin Chiu

Guo-Huei Wu

Min-Hwa Chi

Kuo-Yin Lin

Chung-Fan Chiou

Chi-Yuan Chen

In some embodiments, the present disclosure relates to an integrated chip that includes a first nanosheet field effect transistor (NSFET). The first NSFET includes a first nanosheet channel structure arranged over a substrate, a second nanosheet channel structure arranged directly over the first nanosheet channel structure, and a first gate electrode structure. The first and second nanosheet channel structures extend in parallel between first and second source/drain regions. The first gate electrode structure includes a first conductive ring and a second conductive ring that completely surround outer sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, respectively, and that comprise a first material. The first gate electrode structure also includes a passivation layer that completely surrounds the first and second conductive rings, is arranged directly between the first and second nanosheet channel structures, and comprises a second material different than the first material.

Tuning threshold voltage in nanosheet transitor devices

A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Method and device for boosting performance of FinFETs via strained spacer

An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.

Integrated circuit structure with backside via rail

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.

Gate-all-around structure with self substrate isolation and methods of forming the same

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes semiconductor material layers stacked above a substrate along a first direction and a gate structure wrapping around the semiconductor material layers. The semiconductor structure further includes an epitaxial structure coupled to the semiconductor material layers in a second direction that is different from the first direction and a SiGe-containing layer located below the epitaxial structure. In addition, a material of the SiGe-containing layer is different from a material of the epitaxial structure, the SiGe-containing layer comprises a first portion with a first thickness in the first direction, and a second portion with a second thickness in the first direction, and the second thickness is smaller than the first thickness.

Gate-all around transistor with isolating feature under source/drain

A method of making a semiconductor device includes manufacturing a first bridge pillar; manufacturing a first transistor channel bar and first transistor source/drain electrode, the first transistor S/D electrode electrically connecting to the first bridge pillar; manufacturing a second transistor channel bar and second transistor S/D electrode; manufacturing a first metal electrode, the first bridge pillar connecting the first transistor S/D electrode and first metal electrode; manufacturing a first via connected to the first metal electrode; and manufacturing a first conductive line connected to the first via. The first transistor S/D electrode and the second transistor S/D electrode are spaced apart by a first height, the first metal electrode is separate from the second transistor S/D electrode, the first bridge pillar is separate from the second transistor S/D electrode, and the first bridge pillar has a height in the first direction substantially equal to the first height.

Method of forming semiconductor device having segmented interconnect

Semiconductor device including a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

Semiconductor transistor devices having double-sided interconnect structures

A method includes forming a first semiconductor layer over a substrate; forming a dummy material covering a first sidewall of the first semiconductor layer; forming source/drain epitaxy structures over the substrate and in contact with the first semiconductor layer; forming an interfacial layer on a top surface and a second sidewall of the first semiconductor layer that are uncovered by the dummy material; removing the dummy material to expose the first sidewall of the first semiconductor layer; forming a second semiconductor layer on the first sidewall of the first semiconductor layer after removing the dummy material, in which the second semiconductor layer and the source/drain epitaxy structures have different conductivity types; and forming a gate electrode over the interfacial layer.

Semiconductor device and method for forming the same

A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.

Stacking CMOS structure

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first nanostructure over the substrate. The semiconductor device structure also includes a gate stack over the substrate and surrounding the first nanostructure and a first source/drain layer surrounding the first nanostructure and adjacent to the gate stack. The semiconductor device structure further includes a contact structure surrounding the first source/drain layer. A first portion of the contact structure is between the first nanostructure and the substrate, and the first portion of the contact structure has a first curved top surface facing the first nanostructure.

Semiconductor device structure with nanostructure

Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

Self-aligned metal gate for multigate device

A semiconductor device includes a substrate. The semiconductor device further includes a first gate structure on a first side of the substrate. The semiconductor device further includes a second gate structure on a second side of the substrate, wherein the first side is opposite the second side. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

Method of making amphi-FET structure and method of designing

The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

High-voltage nano-sheet transistor

A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.

Air spacer and capping structures in semiconductor devices

Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first channel structure, a first gate dielectric layer surrounding the first channel structure, and a first metal gate surrounding first gate dielectric layer. The first metal gate includes a first metal layer in direct contact with the first gate dielectric layer and a first metal cap in direct contact with the first gate dielectric layer, wherein the first metal cap is in direct contact with the first metal layer.

Semiconductor device and method of forming thereof

Growing community of inventors

Hsinchu, Taiwan

Ching-Wei Tsai