Tpo Displays Corporation

Toppoly Optoelectronics Corporation

Chimei Innolux Corporation

Ching-Wei Lin

Chueh-Kuei Jan

Meng-Hsun Hsieh

Shih-Chang Chang

Hendrik Klaas Louwsma

Chun-Hsiang Fang

Jing-Chen Huang

The present invention is related to an asymmetric aligned display having asymmetric viewing angles. The present invention provides a dual-view or 3D display capable of displaying two images of unrelated or related content along different directions with asymmetric viewing angles. The asymmetric viewing angles of the display device of the present invention can be realized by the introduction of multiple sub-pixel pitches into a single display. To be more specific, the present invention provides an asymmetric aligned display by realizing the asymmetry design in the sub-pixel itself. Consequently, the angular extends of the respective viewing windows or images displayed along different directions can be different or asymmetrical. The asymmetric aligned display of the present invention is, therefore, capable of displaying images along different directions with asymmetric viewing angles and windows without affecting the outer boundaries of the viewing windows.

Asymmetric viewing angles for a dual view display

Systems and methods for generating reference voltages are provided. A representative system comprises a resistor circuit; a first switch coupled between a first end of the resistor circuit and a first power source; a second switch coupled between the first end of the resistor circuit and a second power source; a third switch coupled to a second end of the resistor circuit; a fourth switch coupled to the second end of the resistor circuit; a first resistor coupled between the first end of the resistor circuit and the first switch; a second resistor coupled between the first end of the resistor circuit and the second switch; a third resistor coupled between the second end of the resistor circuit and the third switch; a fourth resistor coupled between the second end of the resistor circuit and the fourth switch; and a control circuit for controlling the switches.

Systems and methods for generating reference voltages

Display devices for displaying images are provided. A representative display device incorporates a display panel that includes a display pixel and a non-display pixel. The display pixel includes at least one switching thin-film transistor and the non-display pixel includes dummy thin-film transistors. A number of the dummy thin-film transistors exceeds a number of the switching thin-film transistors.

Display device for displaying images involving display pixels and non-display pixels

Systems for displaying images are provided. A representative system incorporates a digital data sampling circuit with N stage data inputs. The first stage flip-flop outputs a first output signal. The second stage flip-flop outputs a second output signal. The first stage sample latch circuit receives digital data according to a first control signal. The first stage logic circuit comprises a first converter for inverting the second output signal and generating a first inverse logic signal, and generates the first control signal according to the first output signal and the first inverse logic signal.

System for displaying image

Systems and methods providing driving voltages to an RGBW display panel. A representative system comprises a data driver with a reference voltage generation circuit that is operative to provide reference voltages according to a white component signal (W) extracted from three color input signals (R,G,B), and a digital-to-analog (D/A) conversion unit that is operative to generate driving voltages according to the reference voltages, the three color input signals and the white component signal.

Systems and methods for providing driving voltages to RGBW display panels

Systems for displaying images are provided. A representative system incorporates a display device that includes a data line operative to provide display signals and sweep signals; a scan line operative to provide scan reset signals; a first capacitor having a first end coupled to the data line for storing charges from the signal line; a first inversion unit having an input end coupled to a second end of the first capacitor, a first supply end coupled to a first voltage source, a second supply end coupled to a second voltage source larger than the first voltage, and an output end; a first reset switch having a first end coupled between the second end of the first capacitor and the input end of the first inversion unit, a second end coupled to the output end of the first inversion unit, and a control end coupled to the scan line; a driving TFT having a control end coupled to the output end of the first inversion unit; and an illuminating unit coupled between a first end of the driving TFT and a third voltage source larger than or equal to the first voltage source.

Systems for displaying images involving reduced mura

An N-channel TFT and OLED display apparatus and electronic device using the same are disclosed. The N-channel TFT comprises a a substrate; an active layer on the substrate, wherein the active layer comprises an N type source region and an N type drain region; a gate dielectric layer on the active layer; and a gate region on the gate dielectric layer. At least a part of the highly-doped source region is located under the gate region, and at least a part of the lightly-doped drain region is located under the gate region.

N-channel TFT and OLED display apparatus and electronic device using the same

A method and circuit for driving LCD are provided. Because the conventional Vcom inversion drive method cannot be applied in a self-aligned process, the power consumption cannot be reduced when the size of the transistor decreases. The method and circuit provided uses two different AC signals to provide different reference voltages for the storage capacitor and the liquid crystal capacitor in a pixel respectively. Therefore, it can be applied to the self-aligned process to reduce the power consumption.

Method and circuit for driving liquid crystal display

Systems for providing driving voltage of display panels. An exemplary system comprises a data driving circuit with a plurality of driving units generating analog voltage to drive corresponding pixels according to digital data signals from a data bus, each comprising a temporary storage unit storing N digital data in sequence according to N control signals in a first period and outputting the N digital data in sequence according to M switching signals in a second period; a digital-to-analog (DA) conversion unit converting the N digital data to N analog voltages in sequence; an analog buffering unit buffering the N analog voltages from the DA conversion unit; and a de-multiplexer outputting the N analog voltages to the corresponding pixels selectively according to an enabling signal.

Systems and methods for providing driving voltages to a display panel

An ESD protection circuit for a charge pump circuit, wherein the charge pump circuit provides a first voltage pin and a second voltage pin, and the absolute value of a voltage provided by the first voltage pin being greater than or equal to the absolute value of a voltage provided by the second voltage pin, and the two voltages have the same phase. The ESD protection circuit comprises a first diode reversely connected between the second voltage pin and ground, and a second diode reversely connected between the second voltage pin and the first voltage pin.

ESD protection circuit for charge pump and electronic device and system using the same

Analog buffers with a precise gate to source voltage compensation and a small DC offset, by storing an input offset voltage to be used as an output offset voltage to reverse the offset in the input. A first source follower at the input end and a second source follower at the output end are both coupled to a switching circuit, wherein the first follower provides an input offset voltage (e.g., |Vgsp|) based on the input voltage (Vin), the second source follower provides an output voltage (Vout) by compensating Vin transmitted through the analog buffer circuit with an output offset voltage (|Vgsn|), and the switching circuit stores and equalizes the output offset voltage to the input offset voltage (|Vgsp|=|Vgsn|), so to obtain an output Vout that is identical to Vin.

Analog buffers composed of thin film transistors

Signal driving circuits with high driving capability and precise analog output voltage level, by outputting analog voltages through analog buffers and directly outputting voltages from digital-to-analog converters in turn. A digital-to-analog converter generates a first analog voltage according to digital data. An output circuit selectively either outputs a second analog voltage according to the first analog voltage by an analog buffer to a load or outputs the first analog voltage to the load directly.

Signal driving circuits

A process for forming a polycrystalline silicon layer includes the following steps. Firstly, at least one seed is formed on a substrate. Then, an amorphous silicon layer is formed on the substrate and overlies the seed. Then, the amorphous silicon layer is irradiated with a laser to melt the amorphous silicon layer. Afterward, the molten amorphous silicon layer is recrystallized to form a polycrystalline silicon layer.

Process for forming polycrystalline silicon layer by laser crystallization

A DC/DC conversion circuit for a display panel. The DC/DC conversion circuit converts an input voltage into a boosted voltage, in which first and second charge pump circuits are coupled to first and second clock signals respectively and output a boosted voltage to a load alternately. Under the control of the first and second clock signals, the first charge pump circuit outputs a first signal to disable the output of the second charge pump circuit or the second charge pump circuit output a second signal to disable the output of the first charge pump circuit.

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Taoyuan, Taiwan

Ching-Wei Lin