Intel Corporation

Other

Ching-Tsun Chou

Robert J Safranek

Robert H Beers

James R Vash

Akhilesh Kumar

Phanindra Mannava

Sujoy Sen

Suresh S Chittor

Oleg Margulis

Kiran A Padwekar

Seungjoon Park

Rajee S Ram

Srinand Venkatesan

Andalib Khan

Youfeng Wu

Naveen Cherukuri

Vineeth Mekkat

Tyler N Sondag

A processor of an aspect includes a decode unit to decode a prior instruction that is to have at least a first context, and a subsequent instruction. The subsequent instruction is to be after the prior instruction in original program order. The decode unit is to use the first context of the prior instruction to determine a second context for the subsequent instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the subsequent instruction based at least in part on the second context. Other processors, methods, systems, and machine-readable medium are also disclosed.

Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instruction

A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.

Eliminating redundant store instructions from execution while maintaining total store order

A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.

Satisfying memory ordering requirements between partial reads and non-snoop accesses

A method and system to avoid multi-ring deadlock. The method includes removing a message on a multi-ring interconnect either with a ring connector associated with the target of the message or by the message's source station such that the message travels no more than one time around the slotted ring interconnect before its removal. The method may also be applied to single ring networks for congestion control.

Scheme for avoiding deadlock in multi-ring interconnect, with additional application to congestion control

In one embodiment, the present invention includes a method for associating and storing a code fragment for each cell of a table for a protocol specification in a semantic mapping corresponding to the table, and automatically generating a formal model for the protocol specification using the table and the semantic mapping. Other embodiments are described and claimed.

Methodology and tools for tabled-based protocol specification and model generation

A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, when a conflict associated with a partial memory access, such as a partial write, is detected, a write-back phase is inserted at the conflict phase to write-back the partial data to a home agent. Examples messages to initiate a write-back phase at a conflict phase include: an Acknowledge Conflict Write-back message to acknowledge a conflict and provide a write-back marker at the beginning of the conflict phase, a write-back marker message before the conflict phase, a write-back marker message within the conflict phase, a write-back marker message after the conflict phase, and a postable message after the conflict phase.

Satisfying memory ordering requirements between partial writes and non-snoop accesses

Methods and apparatus relating to a fairness mechanism for starvation prevention in directory-based cache coherence protocols are described. In one embodiment, negatively-acknowledged (nack'ed) requests from a home agent may be tracked (e.g., using distributed linked-lists). In turn, the tracked requests may be served in a fair order. Other embodiments are also disclosed.

Fairness mechanism for starvation prevention in directory-based cache coherence protocols

A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.

Growing community of inventors

Palo Alto, CA, United States of America

Ching-Tsun Chou