Other

Industrial Technology Research Institute

Toshiba Global Commerce Solutions Holdings Corporation

Ching-Tang Chang

Yi-Sheng Lee

Wei-Yi Hsuan

Tsung-Hsien Lin

Kun-Cheng Wu

Shi-Sheng Shang

Shih-Yin Lin

Dze-chaung Wang

Chien-kuo Tien

Bing-Huang Huang

George Shiang Lai

Chien-Kou V Tien

Systems, methods, and mobile computing devices for purchase of items and delivery to a location within a predetermined communication range are disclosed. According to an aspect, a mobile computing device includes a first communications module having a predetermined communication range and configured to receive an indication of one or more items for purchase and delivery to a location within the predetermined communication range. The mobile computing device also includes a user interface and an item ordering manager. The item ordering manager is configured to receive user input via the user interface for selecting one or more of the items for purchase and delivery to the location within the predetermined communication range. The item ordering manager is also configured to use the communications module to communicate identification of the one or more of the items to a second communications module within the predetermined communication range.

Systems, methods, and mobile computing devices for purchase of items and delivery to a location within a predetermined communication range

A magnetic trigger mechanism is provided. The magnetic trigger mechanism operates in conjunction with a plurality of magnetic sensors. The magnetic trigger mechanism includes: a magnet; a body, with its one side provided with a recess and its other side located near the plurality of magnetic sensors; and a moveable section, provided in the recess in a movable manner, comprising an accommodating space for restraining the magnet therein.

Magnetic trigger mechanism and associated control method

A reorder buffer for an out-of-order issue/execute superscalar microprocessor is composed of a destination register unit, four data units, and a destination tag unit. The destination register and tag units are each made up of content addressable memory shift registers, while the data units are made up of random access memory shift registers which contain partial word operands. When an instruction is decoded, the destination register and tag units generate read and write match signals, respectively, for the data registers. The data registers are associated with corresponding lookup circuits and read/write driver cells. A valid bit is derived from a result byte input, and is used to selectively enable the lookup circuits and read/write driver cells to access the partial word operands in the data registers. Thus, the valid bit, in combination with the read and write match signals, provides the inventive reorder buffer with the ability to independently execute partial word operands in parallel.

Reorder buffer architecture for accessing partial word operands

An improved method and apparatus for buffering and issuing instructions for use with superscalar microprocessors are disclosed. The method comprises the steps of: (a) obtaining an instruction buffer comprising a plurality of entries, each entry comprising a random access memory (RAM) portion and a content addressable memory (CAM) portion for storing result data and source operand tag, respectively, wherein the CAM portion also contains means for linking with an associated RAM portion and the result data contains an instruction; (b) providing a result bus capable of transmitting the result data and a result tag; (c) matching the result tag in the result bus with the source operand tag in the CAM, and writing the result data into the RAM portion of an entry if the result tag in the result bus matches the source operand tag of an associated CAM portion; and (d) issuing ready instructions and changing the source operand tag in a corresponding CAM in such a manner that the entry containing the CAM will be identified as an empty entry so as to all new instruction to be written thereto. Because instructions are stored in the RAM in an out-of-order, a linear systolic array is provided so as to keep the sequence of instructions in order. The linear systolic array, which can be easily compressed, allows the prioritization of instructions for issue among ready instructions, and the handling branch mis-prediction and faults to be implemented.

Method for buffering and issuing instructions for use in

An apparatus for producing in a superscalar pipelined system out-of-order execution and in-order completion of a set of macroinstructions, wherein the set of macroinstructions are translated into a set of microinstructions and the microinstructions are executed by the pipelined system and wherein at least some of said macroinstructions translate into more than one microinstruction, the apparatus including a result completion register having a plurality of entry fields each of which is used to indicate a completion state of a different corresponding microinstruction among the set of microinstructions; an interrupt condition register having a plurality of entry fields each of which is used to specify an occurrence of an interrupt condition during fetching, decoding, and executing a corresponding microinstruction among the set of microinstructions; an instruction size register having a plurality of entry fields which are used to identify locations of boundaries between macroinstructions among the set of microinstructions; a priority encoder which receives input from the result completion register and the instruction size register and which during operation generates an output indicating when all of the microinstructions of a next-in-line macroinstruction have been executed; and a retirement controller which receives the output from the priority encoder and which during operation in response to the output of the priority encoder retires the next-in-line macroinstruction when said output indicates that all of the microinstructions of the next-in-line macroinstruction have been executed.

Method and apparatus for implementing precise interrupts in a pipelined

Growing community of inventors

Taipei, Taiwan

Ching-Tang Chang