Ememory Technology Inc.

Powerchip Semiconductor Corporation

Pufsecurity Corporation

Powerflash Technology Corporation

Ching-Sung Yang

Ching-Hsiang Hsu

Wei-Zhe Wong

Shih-Chen Wang

Hsin-Ming Chen

Shih-Jye Shen

Hau-Yan Lu

Wen-Hao Ching

Chih-Chen Cho

Meng-Yi Wu

Wei-Ren Chen

Yen-Hsin Lai

Te-Hsun Hsu

Chih-Hsun Chu

Chia-Cho Wu

Kung-Hong Lee

Hsiang-Chung Chang

Yung-Hsiang Chen

Cheng-Tung Huang

Jih-Wen Chou

Wei-Chen Chang

Tung-Cheng Kuo

Ming-Chou Ho

Wei-Ming Ku

Chih-Hsin Chen

Cheng-Jye Liu

Yen-Tai Lin

Wen-Hao Lee

Chi-Yi Shao

Hsin-Chou Liu

Yueh-Chia Wen

Yung-Hsiang Liu

Ruei-Ling Lin

Hau-yan Lu

An electronic device and a method for performing permission management of a storage device are provided. The storage device includes multiple storage blocks. The electronic device includes a controller and multiple dedicated interfaces, wherein the multiple dedicated interfaces are coupled to multiple ports of the controller. The controller is configured to perform access control of the storage device. The multiple dedicated interfaces correspond to the multiple storage blocks, and each dedicated interface of the multiple dedicated interfaces is configured to provide a dedicated channel for accessing one of the multiple storage blocks corresponding to said each dedicated interface via the controller.

Electronic device and method for performing permission management of storage device

A method of operating the physically unclonable function (PUF)-based key management system includes upon receiving a key generation request including a parameter, a load balancer dispatching a key generation request including a parameter from an external device according to workloads of a plurality of key management components (KMCs). A KMC having minimum workload among the plurality of KMCs is designated as the key-generation KMC and the key generation request is dispatched thereto, and remaining KMCs of the plurality of KMCs are designated as backup KMCs. The method further includes the key-generation KMC generating a key according to the parameter and a first PUF sequence, transmitting the key and an identifier associated therewith to the backup KMC via a backup channel, and the backup KMC generating a wrapped key according to the key and a second PUF sequence.

Key management system providing secure management of cryptographic keys, and methods of operating the same

A random number generator includes a static random number generator, a dynamic entropy source, a counter and a combining circuit. The static random number generator includes an initial random number pool and a static random number pool to output a static random number sequence from one thereof the initial random number pool and the static random number pool. The dynamic entropy source is used to generate a dynamic entropy bit. The counter is used to generate a dynamic random number sequence according to the dynamic entropy bit. The combining circuit is used to output a true random number sequence to a lively random number pool according to the static random number sequence and the dynamic random number sequence. The static random number pool is updated when the lively random number pool is fully updated.

Random number generator and method of generating output random number

A method and a secure boot control circuit for controlling a secure boot of an electronic device. The method is applicable to the secure boot control circuit, and the electronic device includes the secure boot control circuit. The method includes: checking randomness of an output of an entropy source of the secure boot control circuit to generate a check result; utilizing the entropy source to provide a random number sequence; generating a reference code according to the random number sequence; comparing the reference code with an activation code stored in the secure boot control circuit to generate a comparison result; and determining whether to enable at least one function of the electronic device according to at least one of the check result and the comparison result.

Method and secure boot control circuit for controlling secure boot of electronic device and method for controlling enrollment of electronic device

An encryption key generating engine includes a random number pool, an entangling string generator, and a control circuit. The random number pool stores a plurality of random bits, and values of the plurality of random bits are generated randomly. The entangling string generator provides an entangling string according to an input key. The control circuit is coupled to the random number pool and the entangling string generator. The control circuit retrieves a sequence of random bits from the plurality of random bits stored in the random number pool according to the input key, receive the entangling string from the entangling string generator, and entangle the entangling string with the sequence of random bits to generate a secret key.

High speed encryption key generating engine

The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.

Code generating apparatus and one time programming block

An electronic device having anti-cloning function includes a first critical integrated circuit, which further includes a first security function block configured to authenticate an identity of a second critical integrated circuit in communication with the first critical integrated circuit, wherein the first security function block authenticates the identity of the second critical integrated circuit according to a chip identity of the second critical integrated circuit created using a non-volatile memory (NVM) physically unclonable function (PUF).

Electronic device with self-protection and anti-cloning capabilities and related method

A random number generator device has at least at least a memory unit, a voltage generator, and a control circuit. Each memory unit has two memory cells, one of the two memory cells is coupled to a bias line and a first bit line, and another of the two memory cells is coupled to the bias line and a second bit line. The voltage generator provides the two memory cells a bias voltage, a first bit line voltage and a second bit line voltage via the bias line, the first bit line and the second bit line respectively. The control circuit shorts the first bit line and the second bit line to program the two memory cells simultaneously during a programming period and generates a random number bit according the statuses of the two memory cells during a reading period.

Random number generator device and control method thereof

An integrated capacitance sensing module includes a silicon substrate, a first and a second and a third interlayer dielectric layers, plural conducting layers, a shielding layer, a lower and a upper sensing electrode layers, a protective coating layer. An embedded memory and a sensing circuit are constructed in the silicon substrate. The first interlayer dielectric layer covers the silicon substrate. The plural conducting layers are formed over the first interlayer dielectric layer. The shielding layer is formed over the plural conducting layers. The second interlayer dielectric layer covers the shielding layer. The lower sensing electrode layer is formed over the second interlayer dielectric layer. The third interlayer dielectric layer is formed over the lower sensing electrode layer. The upper sensing electrode layer is formed over the third interlayer dielectric layer. The protective coating layer covers the upper sensing electrode layer.

Integrated capacitance sensing module and associated system

A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.

Memory array with memory cells arranged in pages

An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.

Erasable programmable single-ploy nonvolatile memory

An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.

Anti-fuse memory ultilizing a coupling channel and operating method thereof

A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.

Flash memory apparatus with programming voltage control generators

A one-bit memory cell for a nonvolatile memory includes a bit line and a plurality of serially-connected storage units. The bit line is connected to the serially-connected storage units. Each storage unit includes a first doped region, a second doped region and a third doped region, which are formed in a surface of a substrate. A first gate structure is disposed over a first channel region between the first doped region and the second doped region. The first gate structure is connected to a control signal line. A second gate structure is disposed over a second channel region between the second doped region and the third doped region. The second gate structure is connected to an anti-fuse signal line.

Growing community of inventors

Hsinchu, Taiwan

Ching-Sung Yang