Taiwan Semiconductor Manufacturing Comp. Ltd.

Ching-Sheng Chu

Chern-Yow Hsu

Dun-Nian Yaung

Jen-Cheng Liu

Shih-Chang Liu

Yao-Wen Chang

Wen-De Wang

Ching-Chung Su

Yu-Cheng Tsai

Gung-Pei Chang

Meng-Hsien Lin

Guan-Hua Chen

Chia-Shiung Tsai

The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

High capacitance MIM device with self aligned spacer

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.

Mask transfer method (and related apparatus) for a bumping process

The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond bump disposed on an upper surface of an upper conductive structure. The upper conductive structure overlies a substrate. A buffer layer is disposed along the upper surface of the upper conductive structure. The bond bump comprises a sidewall having a straight sidewall segment overlying a curved sidewall segment.

Bump structure to prevent metal redeposit and to prevent bond pad consumption and corrosion

The present disclosure provides a method for forming a semiconductor structure. The method includes the following operations. A metal layer is formed. An adhesion-enhancing layer is formed over the metal layer by a silicide operation. A dielectric stack is formed over the adhesion-enhancing layer. A trench is formed in the dielectric stack by removing a portion of dielectric stack aligning with the metal layer. A barrier layer is formed conforming to the sidewall of the trench. A high-k dielectric layer is formed conforming to the barrier layer. A contact is formed in the trench and be connected to the metal layer.

Method for forming a semiconductor structure

Various embodiments of the present disclosure are directed towards a semiconductor device structure including a bump structure overlying a bond pad. The bond pad is disposed over a semiconductor substrate. An etch stop layer overlies the bond pad. A buffer layer is disposed over the bond pad and separates the etch stop layer and the bond pad. The bump structure includes a base portion contacting an upper surface of the bond pad and an upper portion extending through the etch stop layer and the buffer layer. The base portion of the bump structure has a first width or diameter and the upper portion of the bump structure has a second width or diameter. The first width or diameter being greater than the second width or diameter.

The present disclosure provides a semiconductor structure, including providing a metal layer, an adhesion-enhancing layer over the metal layer, a dielectric stack over the adhesion-enhancing layer, a contact penetrating the dielectric stack and the adhesion-enhancing layer and connecting with the metal layer, a barrier layer disposed between the contact and the dielectric stack, and a high-k dielectric layer disposed between the contact and the barrier layer.

Semiconductor structure and manufacturing method of the same

The present disclosure relates to a MIM capacitor that includes a composite capacitor top metal (CTM) electrode and a composite capacitor bottom metal (CBM) electrode. The composite CBM electrode includes a first diffusion barrier layer overlying a first metal layer, and the composite CTM electrode includes a second diffusion barrier layer overlying a second metal layer. A dielectric layer is arranged over the composite CBM electrode, underlying the composite CTM electrode. The first and second diffusion barrier layers protect the first and second metal layers from metal that diffuses or moves from a metal line underlying the MIM capacitor to the composite CTM and CBM electrodes during manufacture. A method of manufacturing the MIM capacitor is also provided.

Method for preventing copper contamination in metal-insulator-metal (MIM) capacitors

Some embodiments relate to a metal-insulator-metal (MIM) capacitor, which includes a capacitor a capacitor bottom metal (CBM) electrode, a high k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high k dielectric layer. In some embodiments, the MIM capacitor comprises CTM protective sidewall regions, which extend along vertical sidewall surfaces of the CTM electrode, and protect the CTM electrode from leakage, premature voltage breakdown, or burn out, due to metallic residue or etch damage formed on the sidewalls during one or more etch process(es) used to form the CTM electrode. In some embodiments, the MIM capacitor comprises CBM protective sidewall regions, which extend along vertical sidewall surfaces of the CBM electrode. In some embodiments, the MIM capacitor comprises both CBM and CTM protective sidewall regions.

Growing community of inventors

Baoshan, China

Ching-Sheng Chu