National Chung Cheng University

National Science Council of Republic of China

Ching-Rong Chang

Jinn-Shyan Wang

Ching-Wei Yeh

A low power dynamic logic circuit. By shifting a discharge NMOS transistor of a conventional dynamic logic circuit between an output terminal and a logic block, plus an additional charge and discharge control, the operation speed and power consumption of a dynamic circuit can be effectively improved. Using the charge redistribution to speed up the circuit operation and to reduce the body effect that affects the operation speed, the speed of the novel dynamic logic circuit is enhanced. By transferring the lump capacitor of the charge/discharge, the dynamic power can be effectively reduced. The lower power dynamic logic circuit can be used independently or combined with a conventionally dynamic logic circuit.

Low power dynamic logic circuit

An assembling method for a low-power programmable logic array circuit. The assembling method is capable of reducing delays and unnecessary power consumption. According to the low potential power loss when the dynamic gates in the AND-plane and the OR-plane output a low potential, the high potential power loss when the dynamic gates in the AND-plane and the OR-plane output a high potential and the probability of the dynamic gates outputting a high potential, a selection between new dynamic logic circuit and conventional dynamic circuit is carried out. The conventional dynamic circuit in the AND-plane refers to a conventional dynamic circuit whereas the conventional dynamic circuit in the OR-plane refers to a conventional footless dynamic circuit

Low power programmable logic array assembly

The invention relates to a ROM with four-phase dynamic circuits, featuring at a concept of four-phase operation by fusing and combining pseudo-domino dynamic circuits as well as skill of HS-PDCMOS dynamic circuits. Meanwhile, the invention has improved HS-PDCMOS concept circuit for use in a ROM. Analysis and simulation reveal that the invention is advantageous not only in keeping a compact circuit area but also in evaluation speed and in reducing power dissipation for a ROM.

Growing community of inventors

Chi-Lung, Taiwan

Ching-Rong Chang