Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Ching-Pin Yuan

Ming-Fa Chen

Sung-Feng Yeh

Chen-Hua Douglas Yu

Hsien-Wei Chen

Ching-Hua Hsieh

Yi-Yang Lei

Cheng-Yu Kuo

Hui-Wen Liu

Yu-Ching Lo

Chih-Chia Hu

Sen-Bor Jan

Wei-Jie Huang

Wen-Chih Lin

Tsun-Hsu Chang

A workpiece chuck includes a supporting platform, a vacuum system, and a gas permeable buffer layer. The supporting platform has a supporting surface for holding a workpiece thereon. The vacuum system is disposed under and in gas communication with the supporting platform. The gas permeable buffer layer is disposed over the supporting platform and covers the supporting surface, wherein a hardness scale of the gas permeable buffer layer is smaller than a hardness scale of the supporting platform.

Workpiece chuck, workpiece handling apparatus, manufacturing method of semiconductor package

A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.

Lamination process, and manufacturing method of semiconductor package using a chuck

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Methods of forming semiconductor device packages having alignment marks on a carrier substrate

Chuck, lamination process, and manufacturing method of semiconductor package using the same

A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.

Semiconductor device and method of manufacturing

Method of forming semiconductor device package having testing pads on an upper die

Method of forming semiconductor device package having dummy devices on a first die

Method of forming semiconductor device package having testing pads on a topmost die

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first integrated circuit die, a second integrated circuit die coupled to the first integrated circuit die, and a through-via coupled between a first conductive feature of the first integrated circuit die and second conductive feature of the second integrated circuit die. A conductive shield is disposed around a portion of the through-via.

Semiconductor devices and methods of manufacture thereof

Semiconductor devices and methods of manufacturing thereof

Provided is a 3DIC structure including first and second IC chips and connectors. The first IC chip includes a first metallization structure, a first optical active component, and a first photonic interconnection layer. The second IC chip includes a second metallization structure, a second optical active component, and a second photonic interconnection layer. The first and second IC chips are bonded via the first and second photonic interconnection layers. The first optical active component is between the first photonic interconnection layer and the first metallization structure. The first optical active component and the first metallization structure are bonded to each other. The second optical active component is between the second photonic interconnection layer and the second metallization structure. The second optical active component and the second metallization structure are bonded to each other.

Three-dimensional integrated circuit structure

A semiconductor device includes a first die, a second die bonding to the first die thereby forming a bonding interface, and a pad of the first die and exposed from a polymeric layer of the first die. The semiconductor device further has a conductive material on the pad and extended from the pad in a direction parallel to a stacking direction of the first die and the second die. In the semiconductor device, the conductive material extended to a top surface, which is vertically higher than a backside of the second die, wherein the backside is a surface opposite to the bonding interface.

Semiconductor device and manufacturing method thereof

Growing community of inventors

Hsinchu, Taiwan

Ching-Pin Yuan