United Microelectronics Corp.

Ching-Ming Lee

Wei-Lun Hsu

Te-Yuan Wu

Chih-Chung Wang

Sung-Nien Tang

Wen-Fang Lee

Kuo-Yuh Yang

Ke-Feng Lin

Chih-Jen Huang

Jian-Bin Shiu

Chiu-Ling Lee

Shih-Chieh Pu

Tseng-Hsun Liu

Yu-Hong Huang

Chao-Yuan Su

Chin-Wen Huang

Yu-Ju Yang

Wunn-Shien Liao

Pao-An Chang

Yi-Ming Wang

Chun-Hsiung Peng

Ky Yang

Zheng-Hong Chen

A high voltage semiconductor device includes a substrate, an insulating layer positioned on the substrate, and a silicon layer positioned on the insulating layer. The silicon layer further includes at least a first doped strip, two terminal doped regions formed respectively at two opposite ends of the silicon layer and electrically connected to the first doped strip, and a plurality of second doped strips. The first doped strip and the terminal doped regions include a first conductivity type, the second doped strips include a second conductivity type, and the first conductivity type and the second conductivity type are complementary. The first doped strip and the second doped strips are alternately arranged.

High voltage semiconductor device

A high-voltage semiconductor device is disclosed. The HV semiconductor device includes: a substrate; a well of first conductive type disposed in the substrate; a first doping region of second conductive type disposed in the p-well; a first isolation structure disposed in the well of first conductive type and surrounding the first doping region of second conductive type; and a first drift ring of second conductive type disposed between the first doping region of second conductive type and the first isolation structure.

High-voltage semiconductor device

A method for fabricating a lateral-diffusion metal-oxide semiconductor (LDMOS) device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first region and a second region both having a first conductive type in the semiconductor substrate, wherein the first region not contacting the second region; and performing a thermal process to diffuse the dopants within the first region and the second region into the semiconductor substrate to form a deep well, wherein the doping concentration of the deep well is less than the doping concentration of the first region and the second region.

Lateral-diffusion metal-oxide semiconductor device

A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage.

Method for operating semiconductor device

A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source.

Semiconductor device and method for operating the same

A high-voltage transistor device has a substrate, an isolation structure, a source, a gate, a drain, a plurality of doped regions, a plurality of ion wells, and a first dielectric layer disposed on the substrate. The high-voltage transistor device further has a first conductive layer and a plurality of first field plate rings. The first conductive layer is electrically connected to the drain and at least one of the first field plate rings.

High-voltage MOS transistor device

A phase grating image-sensing device. The device includes a plurality of photodiodes, a smoothing layer, a color filter layer and a plurality of phase gratings. The photodiodes are formed on a substrate and isolated from each other by isolation structures. The smoothing layer covers the photodiodes and the isolation structures. The color filter layer is embedded within the smoothing layer forming a sandwich structure with the smoothing layer. The phase gratings are formed over the smoothing layer positioned at corresponding locations above isolation structures. The phase grating layers produce a constructive interference of light passing through the smoothing layer.

Phase grating image sensing device and method of manufacture

The present invention provides a method for forming capacitor of a dynamic random access memory cell. The method comprises providing a substrate and the word line structures formed thereon. A first dielectric layer is deposited on the substrate and the word line structures. A first polysilicon layer is deposited to form bit line contacts and bit lines. A second dielectric layer is formed on the first dielectric layer and the bit lines. The partial second dielectric layer is removed to form at least a wall structure in the second dielectric layer. The partial second dielectric layer and partial first dielectric layer are removed to form a capacitor contact opening. A second polysilicon is deposited into the capacitor contact opening and on the wall structure and the second dielectric layer. The partial second polysilicon is removed to form a capacitor node whereby a side-wall of the capacitor node is adjacent to the wall structure.

Method for forming capacitor of a DRAM having a wall protection structure

A method of forming a self-aligned stacked capacitor on a substrate having a first insulation layer thereon. A bit line contact and a first section node contact are formed in the first insulation layer, and then a bit line structure is formed over the first insulation layer. The bit line structure includes a bit line, a cap layer and spacers. The bit line and the bit line contact are electrically connected. The cap layer is formed above the bit line while the spacers are formed on the sidewalls of the bit line and the cap layer. A second insulation layer, an etching stop layer and a third insulation layer are sequentially formed over the substrate. An opening is formed in the third insulation layer, the etching stop layer and the second insulation layer to expose a portion of the bit line structure and the first section node contact. A conformal first conductive layer is formed over the interior surface of the opening. The first conductive layer forms a second section node contact as well as a crown-shaped lower electrode. Finally, a conformal dielectric layer and a second conductive layer are sequentially formed over the substrate. The second conductive layer forms the upper electrode of the crown-shaped capacitor.

Growing community of inventors

Miaoli County, Taiwan

Ching-Ming Lee