Dell Products Inc.

Ching-Lung Chao

Shih-Hao Wang

Hung-Tah Wei

Hsin-Chieh Wang

Wei G Liu

Zhengyu Yang

Jayanth Raghuram

Yu-Hsuan Chou

Xi Li

Mukund Purshottam Khatri

Vijay Bharat Nijhawan

Jinsaku Masuyama

William Carl Munger

Po-Yu Cheng

Wai-Ming Richard Chan

Rui Shi

Yiping Zhou

Shih-Hao Shih-Hao Wang

Amber Hokama

Yu-Shuang Liao

A Reliability, Availability and Serviceability (RAS) offload Post-Package Repair (PPR) request system includes a memory system coupled to a Baseboard Management Controller (BMC) device and a Basic Input/Output System (BIOS) subsystem. The BMC device identifies an error in the memory system, retrieves error information associated with the error, uses the error information to generate a Post-Package Repair (PPR) request, and stores the PPR request in a BMC database provided in the BMC device. During an initialization process that occurs subsequent to storing the PPR request in the BMC database, the BMC device retrieves the PPR request and stores it in a shared buffer subsystem. During the initialization process, the BIOS retrieves the PPR request from the shared buffer subsystem, stores the PPR request in a BIOS database provided in the BIOS subsystem, and performs PPR operations on the memory system based on the PPR request stored in the BIOS database.

RAS offload PPR request system

A memory device Post Package Repair (PPR) failure handling system includes a memory device having a first memory subsystem, and a memory management subsystem coupled to the memory device. The memory management subsystem identifies a first PPR request to perform first PPR operations on the first memory subsystem, and performs first PPR operations on the first memory subsystem based on the first current PPR request. The memory management subsystem may determine that the first PPR operations on the first memory subsystem have failed and, in response, increment a first PPR failure counter for the first memory subsystem, If, following the incrementing the first PPR failure counter for the first memory subsystem, the memory management subsystem determines that the first PPR failure counter for the first memory subsystem has reached a PPR failure count threshold, the memory management subsystem disables use of the memory device.

Memory device PPR failure handling system

An information handling system includes multiple dual in-line memory modules (DIMMs) and a basic input/output system (BIOS). The DIMMs form a memory system of the information handling system. The BIOS begins a system boot of the information handling system, and performs a first memory reference code training. Based on the first memory reference code training, the BIOS discovers a bad DIMM of the DIMMs, and stores information associated with the bad DIMM. The BIOS reboots the information handling system. During the reboot, the BIOS retrieves the information associated with the bad DIMM. The BIOS disables a slot associated with the bad DIMM. In response to the slot being disabled, the BIOS performs a second memory reference code training. Based on the second memory reference code training, the BIOS downgrades the memory system to a closest possible DIMM population.

Dual in-line memory module map-out in an information handling system

An address range mirroring system includes a plurality of processing subsystem/memory subsystem nodes that each include a respective processing subsystem coupled to a respective memory subsystem, an operating system provided by at least one of the plurality of processing subsystem/memory subsystem nodes, and a Basic Input/Output System (BIOS) that is coupled to the plurality of processing subsystem/memory subsystem nodes. The BIOS identifies an address range mirroring memory size that was provided by the operating system, and an address range mirroring node usage identification that was provided by the operating system. The BIOS then configures address range mirroring according to the address range mirroring memory size in the respective memory subsystem in each of a subset of the plurality of processing subsystem/memory subsystem nodes, with the subset of the plurality of processing subsystem/memory subsystem nodes based on the address range mirroring node usage identification.

Basic input output system (BIOS)&#x2014;identify memory size or node address range mirroring system

A sub-Non-Uniform Memory Access (sub-NUMA) clustering fault resilient memory system includes an initialization subsystem that is coupled to a processing system and a memory system. The initialization subsystem determines that the processing system and the memory system are configured to provide a plurality of NUMA nodes, allocates a respective portion of the memory system to each of the plurality of NUMA nodes, and configures each respective portion of the memory system to mirror a mirrored subset of that respective portion of the memory system. Subsequently, respective data that is utilized by each of the plurality of NUMA nodes provided by the processing system and the memory system and that is stored in the mirrored subset of the respective portion of the memory system allocated to that NUMA node is mirrored in that respective portion of the memory system.

Sub-NUMA clustering fault resilient memory system

During a power-on self-test (POST), a basic input/output system (BIOS) retrieves an attribute value associated with the persistent memory device, and compares the attribute value to a default value. In response to the attribute value matching the default value, the BIOS may determine that a firmware management protocol was not executed during a previous POST. In response to the attribute value not matching the default value, the BIOS may compare the attribute value to a current firmware version of firmware within the persistent memory device.

Information handling system with mechanism for reporting status of persistent memory firmware update

A PPR memory location reporting system includes BIOS coupled to a non-volatile memory system and a volatile memory system. During boot operations, the BIOS identifies a memory location identifier in the non-volatile memory system for a memory location that is included in the volatile memory system and that is associated with PPR, performs PPR operations on the memory location, and determines that the PPR operations on the memory location have failed. In response to determining that the PPR operations on the memory location have failed, the BIOS stores the memory location identifier in a boot error report table that is configured for use by an operating system to prevent use of the memory location by the operating system, and reserves the memory location identifier in a memory map that is configured for use by the operating system to prevent use of the memory location by the operating system.

Post package repair failure memory location reporting system

An information handling system includes a plurality of persistent memory devices and a basic input/output system (BIOS). The BIOS begins a power-on self-test (POST) of the information handling system. During the POST, the BIOS may call a block input/output (I/O) driver to access a memory region within the first persistent memory device. The access of the memory region within the first persistent memory device is to determine whether the first persistent memory device is a bootable persistent memory device. The BIOS may determine whether blocks of the memory region contain bad memory locations. In response to the memory region containing bad memory locations, the BIOS may return a device error message without performing the access of the blocks of the memory region within the first persistent memory device and may boot to an operating system of the information handling system via another bootable device.

System and method to prevent endless machine check error of persistent memory devices

An information handling system includes a processor, a plurality of dual in-line memory modules (DIMMs), and a basic input/output system (BIOS). During a power-on self-test (POST), the BIOS may read serial presence detect data from each of the DIMMs, determine a total amount of installed memory. The BIOS may determine whether the total amount of the installed memory exceeds a maximum memory capacity of the processor. If so, the BIOS may remove memory capacity of the DIMMs to create a second total amount of the installed memory that is less than the maximum memory capacity of the processor, configure a memory address decode register with the second total amount of the installed memory, and complete the POST.

Information handling system to allow system boot when an amount of installed memory exceeds processor limit

A memory scrubbing system includes a persistent memory device coupled to an operating system (OS) and a Basic Input/Output System (BIOS). During a boot process and prior to loading the OS, the BIOS retrieves a known memory location list that identifies known memory locations of uncorrectable errors in the persistent memory device and performs a partial memory scrubbing operation on the known memory locations. The BIOS adds any known memory locations that maintain an uncorrectable error to a memory scrub error list. The BIOS then initiates a full memory scrubbing operation on the persistent memory device, cause the OS to load and enter a runtime environment while the full memory scrubbing operation is being performed, and provides the memory scrub error list to the OS.

Memory scrub system

A virtual non-volatile memory system includes a BIOS coupled to a non-volatile storage system and a volatile memory system. The BIOS designates a portion of the volatile memory system as a virtual NVDIMM, reserves a portion of the non-volatile storage system for storing virtual NVDIMM data, reports the virtual NVDIMM to an operating system using an ACPI NFIT, and emulates an NVDIMM controller. When a virtual NVDIMM storage event occurs, the BIOS copies data from the portion of the volatile memory system designated as the virtual NVDIMM to the portion of the non-volatile storage system reserved for storing virtual NVDIMM data. When the BIOS subsequently determines that a virtual NVDIMM recovery event has occurred, it copies the data stored in the portion of the non-volatile storage system reserved for storing virtual NVDIMM data to the portion of the volatile memory system designated as the virtual NVDIMM.

Virtual non-volatile memory system

A non-volatile dual in-line memory module (NVDIMM) instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated. The second partition is accessible to the operating system. A processor detects a first bad memory location in the second partition, stores a first system physical address of the first bad memory location to a system bad memory locations list, and stores a first DIMM physical address of the first bad memory location to a first NVDIMM bad memory locations list in the first partition.

System and method to reduce address range scrub execution time in non-volatile dual inline memory modules

Basic input output system (BIOS)&#x2014;identified memory size and node address range mirroring system

During a power-on self-test (POST), the BIOS of an information handling system may read a percentage remaining of a persistent memory device. If the percentage remaining satisfies a threshold, the BIOS may provide a message recommending that the persistent memory device be replaced, or automatically swapping the namespaces between two sets of persistent memory devices based on the write endurance remaining threshold.

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Austin, TX, United States of America

Ching-Lung Chao