Himax Technologies, Inc.

National Yang Ming Chiao Tung University

Ching-Ling Tsai

Tung-Yang Chen

Shih-Fan Chen

Ming-Dou Ker

Cheng-Cheng Yen

Sheng-Fan Yang

Hung-Yi Chen

Jui-Ni Lee

An electrostatic discharge protection (ESD) structure for protecting a core circuit of an integrated circuit from an ESD event received by a conductive pad of the integrated circuit is provided. The ESD protection structure includes a first conductive layer, a clamp device, a first electrical connection part and a second electrical connection part. The first conductive layer is formed below the conductive pad, and includes a first conductive portion, an insulating portion and a second conductive portion. The insulating portion is surrounded by the first conductive portion and the second conductive portion. The first conductive portion is electrically connected between the conductive pad and the second conductive portion. The clamp device is arranged for clamping the ESD event. The first electrical connection part is coupled between the first conductive portion and the clamp device. The second electrical connection part is coupled between the second conductive portion and the core circuit.

Electrostatic discharge (ESD) protection structure utilizing floor plan design to protect integrated circuit from ESD event, and related integrated circuit and ESD protection method

A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.

Self-reset transient-to-digital convertor and electronic product utilizing the same

A method of simulating an electrostatic discharge (ESD) circuit layout is disclosed. A netlist of an electronic circuit is pre-simulated. A circuit layout, including an ESD circuit layout, is accordingly generated. Parasitic is extracted according to the generated circuit layout. The ESD circuit layout is post-simulated according to an ESD waveform and a result of the parasitic extraction.

Method of simulating an ESD circuit layout

A method for predicting and debugging electromagnetic interference (EMI) characteristics of an integrated circuit (IC) system includes the following steps: selecting a frequency domain range according to transformed raw data of the IC system to generate a blocking frequency analysis result, wherein the transformed raw data are transformed by a time-frequency waveform transformation; setting criteria data; comparing the blocking frequency analysis result with the criteria data to generate at least one comparison result; and generating a pass analysis report when a processing unit determines that each comparison result is passed; otherwise, executing an EMI design time-frequency analysis.

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Tainan, Taiwan

Ching-Ling Tsai