Macronix International Co., Ltd.

Tsinghua University

Ching-Lin Chan

Cheng-Chi Lin

Shih-Chin Lien

Chen-Yuan Lin

Shyi-Yuan Wu

Yu-Chin Chien

Chien-Hong Cheng

Yu-Wei Chang

Shuo-Lun Tu

Ming-Tung Lee

Chin-Hsien Chen

Lun-Chia Hsu

Chin-Wei Chang

Chin-Shien Lu

A semiconductor device is provided. The semiconductor device includes a first doped region and a second doped region of a first conductive type and a third doped region of a second conductive type located in a substrate. The second doped region is located at a side of the first doped region. A top-view pattern of the second doped region has at least one recess portion. The third doped region is located between the first doped region and the second doped region. A top-view pattern of the third doped region has at least one protruded portion corresponding to the at least one recess portion.

Semiconductor device

A high voltage semiconductor device including a P type substrate, a high voltage N type well, a first P type well, a drift region, and a P type doping layer is provided. The high voltage N type well and the P type doping layer, which is formed in a region located below the first P type well and the drift region, are formed in the P type substrate. The first P type well is formed in the high voltage N type well. A bottom of the first P type well and a bottom of the P type doping layer are separated from a surface of the P type substrate by a first depth and a second depth larger than the first depth, respectively. The drift region is formed in the high voltage N type well and extending down from the surface of the P type substrate.

High voltage semiconductor device

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a drift region formed in the high-voltage well, a drain region formed in the high-voltage well and spaced apart from the drift region, and a buried region having the first conductivity type formed in the high-voltage well between the drift region and the drain region.

Semiconductor device having buried region and method of fabricating same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.

Semiconductor structure and method for forming the same

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a high-voltage doped region having the first conductivity type and disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart from the high-voltage doped region, a source region disposed in the high-voltage doped region, a first gate structure disposed above a first side portion of the high-voltage doped region between the source region and the drain region, and a second gate structure disposed above a second and opposite side portion of the high-voltage doped region.

Semiconductor device having gate structures and manufacturing method thereof

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a drift region formed in the high-voltage well, and a buried layer having the first conductivity type formed below the high-voltage well and vertically aligned with the drift region.

Semiconductor device having buried layer

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a source well having the first conductivity type disposed in the high-voltage well, a drift region disposed in the high-voltage well and spaced apart from the source well, and a gradient implant region having the second conductivity type and disposed in the high-voltage well between the source well and the drift region.

Semiconductor device having gradient implant region and manufacturing method thereof

A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a deep well, a first well, a first doped electrode region, a second doped electrode region and a high voltage threshold voltage channel region. The substrate has a first type conductivity. The deep well is formed in the substrate and has a second type conductivity opposite to the first conductivity. The first well is formed in the deep well and has at least one of the first type conductivity and the second type conductivity. The first and the second doped electrode regions are formed in the first well. The second doped electrode is adjacent to the first doped electrode and has the second conductivity. The high voltage threshold voltage channel region is formed in the first well and extending down from the surface of the substrate.

Semiconductor device and manufacturing method and operating method for the same

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a source well having the first conductivity type and formed in the high-voltage well, a source region formed in the source well, an isolation layer formed above the high-voltage well and spaced apart from the source well, a gate layer formed above the substrate and continuously extending from above an edge portion of the source well to an edge portion of the isolation layer, and a metal layer formed above the substrate and the isolation layer. The metal layer includes a first metal portion overlapping an edge portion of the gate layer and a side portion of the isolation layer, a second metal portion overlapping and conductively contacting the gate layer, and a third metal portion overlapping and conductively contacting the source region.

Semiconductor device having metal layer and method of fabricating same

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a source well having the first conductivity type and disposed in the high-voltage well, a drift region disposed in the high-voltage well and spaced apart from the source well, and a deep implantation region having the first conductivity type and disposed in the high-voltage well between the source well and the drift region.

Semiconductor device having deep implantation region and method of fabricating same

A method of manufacturing a semiconductor structure with a high voltage area and a low voltage area is provided. The method includes the following steps: providing a substrate of a first conductivity type; forming a second doped region of a second conductivity type in the substrate by a first implantation; forming a first doped region of a first conductivity type in the second doped region by a second implantation; forming an insulating layer on the substrate; forming a resistor on the insulating layer, wherein the resistor is electrically connecting the high voltage area and the low voltage area; and forming a conductor electrically connected to the resistor. The step of forming a first doped region defines the high voltage area and the low voltage area.

Method of manufacturing semiconductor structure

A junction field effect transistor is disclosed. The junction field effect transistor includes a first doped region and a second doped region. The first doped region includes a source and a drain. The second doped region includes a gate. The first doped region and the second doped region have a U-shape PN junction there between. The U-shape PN junction is between the source and the drain.

Junction field effect transistor

A 6H-indeno[2,1-b]quinoline derivative has a structure of formula (I). Each of Arand Aris a member selected from the group consisting of a substituted or non-substituted aryl group and a substituted or non-substituted heteroaryl group and Rto Rare substituents. The 6H-indeno[2,1-b]quinoline derivative of the present invention is provided with thermal stability. Chemical compounds of the present invention are adequate for the materials of the light-emitting layer of an OLED device with high device performance.

6H-indeno[2,1-B]quinoline derivative and organic light emitting diode using the same

An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor.

Methods of manufacturing a semiconductor device having varying p-top and n-grade regions

Provided is a semiconductor device including a substrate, an isolation structure, a gate structure, source and drain regions and a conductive layer. The source and drain regions are disposed in the substrate. The isolation structure is disposed between the source and drain regions. The gate structure is disposed on the substrate between the source and drain regions. The conductive layer is disposed on the substrate, extends from above the source region to above the isolation structure and is electrically connected to the source region. The substrate has first and second areas. The source region in the second area has a border curvature greater than that in the first area. The width of the portion of the conductive layer covering the isolation structure in the second area has a width greater than that in the first area.

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Yunlin County, Taiwan

Ching-Lin Chan