Taiwan Semiconductor Manufacturing Comp. Ltd.

Ching-Hwanq Su

Chung-Chiang Wu

Da-Yuan Lee

Chia-Ching Lee

Cheng-Lung Hung

Yu-Sheng Wang

Chi-Cheng Hung

Cheng-Yen Tsai

Wei-Chin Lee

Shih-Hang Chiu

Weng Chang

Ru-Shang Hsiao

Kuan-Ting Liu

Ying Hsin Lu

Hsueh Wen Tsau

Pin Chia Su

Zoe Chen

Chih-Wei Chang

Hung-Chin Chung

Ya-Huei Li

Ling-Sung Wang

Hsin-Yi Lee

Ming-Chi Huang

Chun-Wen Nieh

Tai-Wei Hwang

Huicheng Chang

Ming-Hsing Tsai

Yu-Ting Lin

Xiong-Fei Yu

Li-Wei Chu

Che-Hao Chang

Hung-Yi Huang

Ji-Cheng Chen

Kun-Yu Lee

I-Shan Huang

Chih-Cherng Jeng

Yin-Chuan Chuang

Yu-Hsiang Liao

Shu-Yuan Ku

Chih-Chang Hung

Wei-Ming You

Min-Hsiu Hung

I-Wei Yang

Liang-Yueh Ou Yang

Yi-Hsiang Chao

Kan-Ju Lin

Kuan-Yu Yeh

Chien-Hao Chen

Hsien-Ming Lee

Huang-Yi Huang

Chih-Kang Chao

Ting-Siang Su

Pohan Kung

Yu-Shen Shih

Kuo-Cheng Lee

Kei-Wei Chen

Shiu-Ko JangJian

Ying-Lang Wang

Chih-Mu Huang

Yu-Ku Lin

Jung-Chi Jeng

Hung-Jen Lin

Shih-Ho Lin

Chih-Fu Chang

Chun-Yuan Chou

Sung-Hsin Yang

Yen-Hsiu Chen

Wen-Hsin Chan

Po-Jen Shih

Hsueh-Wen Tsau

Yen-Hsung Ho

Chao-Lung Chen

Ming-Chu King

Cheng-Jung Sung

Yan-Hua Lin

Chi-Hung Chuang

Yun Chen Chang

Lan Fang Chang

Ru-shang Hsiao

Chung-Yi Su

Fu-Sheng Guo

Shang-Chin Sung

Chen-Bin Lin

The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.

Circuit structure with gate configuration

A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

FinFET structures and methods of forming the same

A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.

Integration of multiple transistors having fin and mesa structures

A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.

Method of manufacturing gate structure and method of manufacturing fin-field effect transistor

Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

Pre-deposition treatment for FET technology and devices formed thereby

Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

Semiconductor device and method of manufacture

A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

Gate electrode having a work-function layer including materials with different average grain sizes

A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

Contact plug with impurity variation

A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.

Structure for metal gate electrode and method of fabrication

A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

Metal gate structures and methods of fabricating the same in field-effect transistors

Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

Geometry for threshold voltage tuning on semiconductor device

A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a barrier layer. The work function layer is surrounded by the gate dielectric layer. The metal layer is disposed over the work function layer. The barrier layer is surrounded by the work function layer and surrounds the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure.

Gate structure, fin field-effect transistor, and method of manufacturing fin-field effect transistor

In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

Semiconductor devices having dipole-inducing elements

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Tainan, Taiwan

Ching-Hwanq Su