Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Ching-Hung Wang

Yeong-Jyh Lin

Chung-Yi Yu

Ching I Li

Ru-Liang Lee

De-Yang Chiou

Sz-Fan Chen

Han-Jui Hu

Yeur-Luen Tu

Ping-Yin Liu

Tzu-Wei Yu

Chien-Hung Liu

Jyun-Siang Huang

Ying-Tso Chen

Chia-Wen Cheng

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes performing a bonding process to bond a first semiconductor substrate to a second semiconductor substrate. A shift measurement process is performed on the first and second semiconductor substrates. The shift measurement process includes moving a plurality of substrate pins from a plurality of initial positions to a plurality of measurement positions. The plurality of substrate pins are disposed outside of perimeters of the first and second semiconductor substrates. A shift value is determined between the first semiconductor substrate and the second semiconductor substrate based at least in part on a difference between the plurality of initial positions and the plurality of measurement positions.

Mechanical wafer alignment detection for bonding process

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.

Photolithography alignment process for bonded wafers

Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process. An OVL shift is determined between the first wafer and the second wafer based on a comparison between the first parameters associated with the wafer pins during the alignment process and the second parameters associated with the wafer pins during the OVL measurement process.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.

Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.

Method for alignment, process tool and method for wafer-level alignment

A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.

Growing community of inventors

Hsinchu, Taiwan

Ching-Hung Wang