Taiwan Semiconductor Manufacturing Comp. Ltd.

Ching-Hui Ma

Jen-Cheng Liu

Chao-Cheng Chen

Hun-Jan Tao

Tsang-Jiuh Wu

Li-Chih Chao

Yi-Chen Huang

Hui-Chang Yu

Jun-Lung Huang

Yin-Shen Chu

Li-Chih Chaio

Hong-Ming Chen

A method of reducing a charge on a substrate to prevent an arcing incident in a subsequent etch process is described. A patterned substrate is fastened to a chuck in a process chamber. A discharge process is performed that includes the three steps of (a) coupling the chuck to a 0 volt connection, (b) generating a plasma, and (c) coupling the chuck to a high voltage connection. The three steps are carried out in any sequence. An inert gas or an inert gas and an etching gas are flowed into the chamber during the discharge sequence. Alternatively, a fluorocarbon CFHor a fluorocarbon and a gas such as O, H, N, NO, CO, CO, He or Ar is flowed into the chamber during the discharge sequence. The method is compatible with batch or single wafer processes and is extendable to etching low k dielectric layers with poor thermal conductivity.

In-situ discharge to avoid arcing during plasma etch processes

A method for improving a photolithographic patterning process to avoid undeveloped photoresist contamination in a semiconductor manufacturing process including providing a first semiconductor feature having an anisotropically etched opening including sidewalls. The first semiconductor feature further provide an overlying photoresist layer photolithographically patterned for anisotropically etching a second semiconductor feature opening overlying and encompassing the first semiconductor feature; blanket depositing a polymeric passivation layer over the overlying photoresist layer including covering at least a portion of the sidewalls including polymeric containing residues; and, removing the polymeric passivation layer including a substantial portion of the polymeric containing residues from at least a portion of the sidewalls prior to anisotropically etching the second semiconductor feature.

Method for removing polymeric residue contamination on semiconductor feature sidewalls

A novel etching method for preventing spiking and undercutting of an ultra low-k material layer in damascene metallization is described. A region to be contacted is provided in or on a semiconductor substrate. A liner layer is deposited overlying the region to be contacted. An ultra low-k dielectric layer is deposited overlying the liner layer. A damascene opening is etched through the ultra low-k dielectric layer to the liner layer overlying the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, high power, and low pressure. The liner layer within the damascene opening is etched away to expose the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, low power, and low pressure to complete formation of a damascene opening in the fabrication of an integrated circuit device.

Prevention of spiking in ultra low dielectric constant material

Growing community of inventors

Tainan, Taiwan

Ching-Hui Ma