Taiwan Semiconductor Manufacturing Comp. Ltd.

Epistar Corporation

Opto Tech Corporation

Ching-Hui Chen

Mirng-Ji Lii

Sheng-Yu Wu

Chin-Yu Ku

Hon-Lin Huang

Chien-Hung Kuo

Chao-Yi Wang

Shang-Yun Tu

Chung-Shi Liu

Hung-Jui Kuo

Alexander Kalnitsky

Ming-Che Ho

Yi-Wen Wu

Kai-Di Wu

Chun-Mao Chiu

Zi-Zhong Wang

Ming-Da Cheng

Chen-Shien Chen

Wei-Hung Lin

Ching-Wen Hsiao

Kuo-Chio Liu

Chang-Jung Hsueh

Chen-En Yen

Cheng-Lung Yang

Chin Wei Kang

Cheng Jen Lin

Kai Jun Zhan

Feng Wei Kuo

Wen-Shiang Liao

Hsing-Kuo Hsia

Chien-Liang Yeh

Chien-Feng Chang

Jacob C Tarn

Ju-Yuan You

Yuh-Sen Chang

Kio-Chio Liu

Chih-Chia Lin

A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.

Semiconductor device

A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.

Display device and manufacturing method thereof

A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

Multi-layer structures and methods of forming

A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.

Forming bonding structures by using template layer as templates

A device includes a ground plane electrically connected to a proximal end of at least one conductive pillar and an antenna pad substantially parallel to the ground plane, wherein the antenna pad is separated from a distal end of the at least one conductive pillar by a dielectric pad having a first dielectric constant, wherein the ground plane, the at least one conductive pillar, and the dielectric pad surround an antenna cavity filled with a dielectric fill material having a second dielectric constant different from the first dielectric constant.

Integrated patch antenna having insulating substrate with antenna cavity and high-K dielectric

A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.

Semiconductor device and bump formation process

Conductive structures and the redistribution circuit structures are disclosed. One of the conductive structures includes a first conductive layer and a second conductive layer. The first conductive layer is disposed in a lower portion of a dielectric layer, and the first conductive layer includes an upper surface with a protrusion at an edge. The second conductive layer is disposed in an upper portion of the dielectric layer and electrically connected to the first conductive layer. An upper surface of the second conductive layer is conformal with the upper surface of the first conductive layer.

Conductive structures and redistribution circuit structures

Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

Semiconductor devices

Redistribution circuit structures and methods of forming the same are disclosed. One of the redistribution circuit structures includes a first conductive structure, a dielectric layer and a second conductive structure. The dielectric layer is disposed over and exposes a portion of the first conductive structure. The second conductive structure is disposed in the dielectric layer to electrically connect to the first conductive structure, and includes a first conductive layer and a second conductive layer disposed on and electrically connected to the first conductive layer. The first conductive layer includes a main portion and a conductive protrusion, the conductive protrusion is disposed on an entire edge of an upper surface of the main portion, and a top of the conductive protrusion is higher than the upper surface of the main portion.

Redistribution circuit structures and methods of forming the same

A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region. The micro bump has a first portion on the pad region and a second portion on the first portion. The first portion and the second portion have different widths. The first portion has a first width and the second portion has a second width. The first width is larger or smaller than the second width. The micro bump includes nickel and gold. The semiconductor device also includes a passivation layer overlying a portion of the pad region.

A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump.

Semicondcutor device and manufacturing method thereof

A semiconductor structure includes an interconnect structure, at least one first metal pad, at least one second metal pad, at least one first bump, at least one second bump, at least one photosensitive material, and a bonding layer. The first metal pad and the second metal pad are disposed on and electrically connected to the interconnect structure. The first bump is disposed on the first metal pad. The second bump is disposed on the second metal pad. The photosensitive material is disposed on the first bump. The bonding layer is in contact with the photosensitive material and the second bump. The photosensitive material is disposed between the first bump and the bonding layer.

Semiconductor structure and manufacturing method thereof

Growing community of inventors

Hsinchu, Taiwan

Ching-Hui Chen