Sandisk Technologies Inc.

Micron Technology Incorporated

Cypress Semiconductor Corporation

Western Digital (fremont), Inc.

Spansion Llc.

Ching-Huang Lu

Yingda Dong

Vinh Diep

Ashish Kumar Baraskar

Zhenming Zhou

Wei Zhao

Liang Pang

Hong-Yan Chen

Lei Xue

Murong Lang

Simon Siu-Sing Chan

Zhengyi Zhang

Yanli Zhang

Yu-Chung Lien

Vinh Q Diep

James K Kai

Hidehiko Shiraiwa

Johann Alsmeier

Rinji Sugino

Pitamber Shukla

Jiahui Yuan

Tao Pan

Yan Chen

Lien-Chang Wang

Zhenyu Lu

Donghong Li

Lieping Zhong

Kenichi Ohtsuka

Ronit Roneel Prakash

Hongzhou Jiang

Raghuveer S Makala

Jian Feng Chen

Jayavel Pachamuthu

Henry Chin

Henry Chien

Jun Wan

Simon S Chan

Ying Hong

Tien-Chien Kuo

Changyuan Chen

Murshed Chowdhury

Weimin Si

Han-Ping Chen

Nagendra Prasad Ganesh Rao

Jinwen Wang

Jianxin Fang

Jiun-Horng Lai

Hoon Cho

Xiangyu Yang

Tomoharu Tanaka

Yoshiaki Fukuzumi

Hiroyuki Ogawa

Rahul Sharangpani

George Matamis

Huai-Yuan Tseng

Fei Zhou

Eric N Lee

Deping He

Akira Goda

Jinqiu Zhang

Scott Anthony Stoller

Anubhav Khandelwal

Fulvio Rori

Shih-Chung Lee

Shuji Tanaka

Zhongguang Xu

Devin M Batutis

Cynthia Hsu

Jixin Yu

Sateesh Koka

Daxin Mao

Somesh Peri

Nan Lu

Xianzhong Zeng

Xiaotian Zhou

Takaaki Iwai

Xiaoyu Yang

Piyush Girish Sagdeo

Rajdeep Gautam

Matthias Baenninger

Sayako Nagamine

Chun-Hung Lai

Yunhe Huang

Wenguang Shi

Jeffrey Ming-Hung Tsai

Wencheng Su

Swaroop Kaza

Avinash Rajagiri

Chengkuan Yin

Yang Xiang

Makoto Koto

Yuichi Ikezono

Chung-Yao Pai

Wai Ying Lo

Aman Gupta

Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.

Multi-stage erase operation of memory cells in a memory sub-system

A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.

Fast program recovery with reduced programing disturbance in a memory device

Methods, systems, and apparatuses include moving a portion of memory to a garbage pool in response to determining that the portion of memory is invalid. The portion of memory is erased in response to determining that the portion of memory is invalid. A request to move an additional portion of memory to a free pool from the garbage pool is received. A free pool includes a queue including erased portions of memory, which serve as next portions of memory to fulfill subsequent cursor requests. The erased portion of memory is moved from the garbage pool to the free pool.

Optimizing data reliability using erase retention

Control logic in a memory device causes a program voltage to be applied to a selected data wordline of a plurality of wordlines of a block of a memory array for a pulse duration period during a programming operation. The control logic further causes a first pass voltage to be applied to one or more unselected data wordlines of the plurality of wordlines of the block for the pulse duration period and causes a second pass voltage to be applied to a last unselected data wordline of the plurality of wordlines of the block for at least a first portion of the pulse duration period, wherein the second pass voltage has a lower magnitude than the first pass voltage.

Program scheme for edge data wordlines in a memory device

A program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. During a program verify operation of the program operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. A pass through read voltage level associated with the target wordline is identified. During the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline or a second wordline, wherein the pass through read voltage level is the read voltage level reduced by an offset value.

Corrective program verify operation with improved read window budget retention

A memory device includes a memory array comprising memory cells associated with a plurality of wordlines control logic that is to perform operations including: causing memory cells of a physical unit of the memory array to be programmed starting at a second wordline, which is adjacent to a first wordline of the memory array, and proceeding sequentially through a plurality of sequentially-ordered wordlines of the physical unit, wherein the first wordline is associated with memory cells that are adjacent to one or more select gate (SG) transistors of the memory array, and the sequentially-ordered wordlines are numbered according to a distance away from the one or more SG transistors; and at least one of after the memory cells associated with the second wordline are programmed or after completion of programming the physical unit, causing the memory cells associated with the first wordline to be programmed.

Out-of-order programming of first wordline in a physical unit of a memory device

Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A sensing time is determined using the cycle number and the group. The command is executed using the sensing time.

Adaptive sensing time for memory operations

A read is initiated with respect to a target cell. A pair of adjacent cells includes a first cell and a second cell each adjacent to the target cell. First cell state information is obtained for the first cell and second cell state information is obtained for the second cell. A state information bin is determined by applying a pre-defined operation to the first cell state information and the second cell state information of the respective pair of adjacent cells. The target cell is assigned to the state information bin. Each state information bin defines a read level offset for reading the target cell.

Corrective reads with improved recovery from data retention loss

A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.

Low stress refresh erase in a memory device

Control logic in a memory device receives a request to perform a memory access operation on a memory array of the memory device and determines an operating temperature of the memory device. The control logic further modifies a default magnitude of a source voltage signal based on the operating temperature to a form a modified source voltage signal, causes the modified source voltage signal to be applied to the memory array, and performs the memory access operation on the memory array.

Source bias temperature compensation for read and program verify operations on a memory device

In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

Memory read operation using a voltage pattern based on a read command type

Memory systems with flexible erase suspend-resume operations are described herein. In one embodiment, a memory device is configured to receive an erase suspend command while a first erase pulse of an erase operation is at a flattop voltage. In response, the memory device suspends the erase operation. The memory device further resumes the erase operation such that a second erase pulse of the erase operation is ramped to the flattop voltage. Absent intervening erase suspend operations, erase operations of the memory device can include a single erase pulse that remains at the flattop voltage for a total duration. A first total duration plus a second total duration the first and second erase pulses, respectively, remain at the flattop voltage remains less than or equal to the total duration the single erase pulse remains at the flattop voltage.

Memory systems with flexible erase suspend-resume operations, and associated systems, devices, and methods

Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.

Enhanced gradient seeding scheme during a program operation in a memory sub-system

A memory device comprising a memory array and control logic operatively coupled with the memory array. The control logic is to: detect a program operation directed at a selected wordline of multiple wordlines of the memory array; determine, during an initial phase of the program operation, whether a program voltage being applied to the selected wordline satisfies a threshold program voltage; add, in response to the program voltage not satisfying the threshold program voltage, a base offset voltage to an initial pass voltage to generate a higher pass voltage, the initial pass voltage being a percentage of an initial program voltage; and cause the higher pass voltage to be applied to a remainder of the multiple wordlines other than the selected wordline.

Selective increase and decrease to pass voltages for programming a memory device

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining whether a temperature offset value of the segment satisfies a threshold criterion associated with a program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.

Adaptive enhanced corrective read based on write and read temperature

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Fremont, CA, United States of America

Ching-Huang Lu