Taiwan Semiconductor Manufacturing Comp. Ltd.

Ching-Hua Hsieh

Chung-Shi Liu

Chih-Wei Lin

Hsiu-Jen Lin

Ming-Da Cheng

Wei-Yu Chen

Hao-Jan Pei

Chen-Hua Douglas Yu

Chih-Chiang Tsao

Chia-Shen Cheng

Shau-Lin Shue

Chia-Lun Chang

Sheng-Hsiang Chiu

Sheng-Feng Weng

Cheng-Lin Huang

Chien-Ling Hwang

Hsuan-Ting Kuo

Shing-Chao Chen

Shing-Chyang Pan

Huang-Yi Huang

Meng-Tse Chen

Chih-Chien Chi

Szu-Ping Tung

Cheng-Ting Chen

Wei-Hung Lin

Yu-Peng Tsai

Yi-Yang Lei

Hao-Yi Tsai

Pei-Hsuan Lee

Li-Lin Su

Jing-Cheng Lin

Kuei-Wei Huang

Mong-Song Liang

Han-Ping Pu

Chao-Wen Shih

Chih-Hua Chen

Yu-Chih Huang

Tsung-Hsien Chiang

Albert Wan

Chao-Wei Li

Chuei-Tang Wang

Chung-Hao Tsai

Chun-Cheng Lin

Hsien-Ming Lee

Yu-Hao Chen

Ying-Jui Huang

Alexander Kalnitsky

Chung-Chi Ko

Ming-Hsing Tsai

Chin-Yu Ku

Chih-Hsuan Tai

Kuo-Chio Liu

Hsueh Wen Tsau

Hsin-Hung Liao

Tzu-Chun Tang

Chao-Hsien Peng

Ting-Ting Kuo

Huang-Ming Chen

Kuo-Chung Yee

Chien Ling Hwang

Chun-Hui Yu

Yu-Wei Lin

Kuo-Lung Pan

Mei-Ling Chen

Syun-Ming Jang Jang

Wei-Cheng Wu

Yu-Chia Lai

Yao-Jen Chang

Neng-Jye Yang

Hao-Cheng Hou

Chia-Hung Liu

Kai-Fung Chang

Jung-Wei Cheng

Ai-Tee Ang

Shih-Peng Tai

Der-Chyang Yeh

Tin-Hao Kuo

An-Jhih Su

Yu-Hsiang Hu

Kai-Chiang Wu

Jiun Yi Wu

Tai-Chun Huang

Chii-Ming M Wu

Ming-Che Ho

Hung-Wen Su

Chih-Hang Tung

Chun-Lin Lu

Tung-Liang Shao

Ming Hung Tseng

Yi-Li Hsiao

Kuei Shun Chen

Kuo Lung Pan

Tzu-Sung Huang

Chih-Hsiang Yao

Minghsing Tsai

Cheng-I Huang

Po-Yuan Teng

Chien-Hsun Chen

Tsai-Tsung Tsai

Su-Chun Yang

A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.

Lamination process, and manufacturing method of semiconductor package using a chuck

A package includes a redistribution structure, a bridge die, conductive pillars, connectors, a first die, first solder joints, and second solder joints. The bridge die includes a substrate, a dielectric layer disposed on the substrate, and routing patterns embedded in the dielectric layer. The conductive pillars are coupled to the redistribution structure at a position that is laterally offset from the bridge die. The connectors are coupled to the bridge die and the redistribution structure, such that the bridge die is electrically coupled to the redistribution structure through at least the connectors. The first solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the bridge die. The second solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the conductive pillars.

Package and manufacturing method thereof

A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.

Staggered metal mesh on backside of device die and method forming same

A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Package structure

A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

Semiconductor device and method of manufacture

An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Integrated circuit package and method

A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.

Integrated fan-out packages and methods of forming the same

A manufacturing method of a package system includes: providing a base plate with a first thermal interface material (TIM) layer; placing a semiconductor package on the first TIM layer over the base plate, wherein the semiconductor package comprises a plurality of packaging units arranged in an array and a plurality of electrical connectors surrounding the array of the plurality of packaging units; stacking a gasket and a top plate on the array of the plurality of packaging units, wherein the gasket is interposed between the top plate and the array of the plurality of packaging units; and securing the top plate, the gasket, the plurality of packaging units, and the base plate together through a plurality of fasteners, wherein each of the plurality of fasteners is arranged at a gap between two of the adjacent packaging units.

Package system and manufacturing method thereof

A method includes forming an insulating layer over a package. The package has a plurality of locations where openings are subsequently formed. A first laser shot is performed, location by location, on each of the locations across the package. A first laser spot of the first laser shot overlaps with each of the locations. The first laser shot removes a first portion of the insulating layer below the first laser spot. Another laser shot is performed, location by location, on each of the locations across the package. Another laser spot of the another laser shot overlaps with each of the locations. The another laser shot removes another portion of the insulating layer below the another laser spot. Performing the another laser shot, location by location, on each of the locations across the package is repeated multiple times, until desired portions of the insulating layer are removed.

Method for laser drilling process for an integrated circuit package

In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.

Methods of forming semiconductor packages

Provided is a package structure including a first redistribution layer (RDL) structure, a die, a circuit substrate, and a first thermoelectric cooler. The RDL) structure has a first side and a second side opposite to each other. The die is disposed on the first side of the first RDL structure. The circuit substrate is bonded to the second side of the first RDL structure through a plurality of first conductive connectors. The first thermoelectric cooler is between the first RDL structure and the circuit substrate, wherein the first thermoelectric cooler includes at least a N-type doped region and at least a P-type doped region.

Package structure having thermoelectric cooler

A molded semiconductor device includes a semiconductor device and a molding material encapsulating the semiconductor device, wherein an upper surface of the molding material is substantially coplanar with an upper surface of the semiconductor device and comprises a groove at least partially surrounding the upper surface of the semiconductor device.

Molded semiconductor device and manufacturing method of molded semiconductor device

A package structure including a semiconductor die, an encapsulant, a redistribution structure, and a through insulating via is provided. The first redistribution structure includes an insulating layer and a circuit layer. The semiconductor die is disposed on the first redistribution structure. The semiconductor die includes a semiconductor base, through semiconductor vias, a dielectric layer, and bonding connectors. Through semiconductor vias penetrate through the semiconductor base. The dielectric layer is disposed on a backside of the semiconductor base. The dielectric layer of the semiconductor die is bonded with the insulating layer of the first redistribution structure. The bonding connectors are embedded in the dielectric layer and connected to the through semiconductor vias. The bonding connectors of the semiconductor die are bonded with bonding pads of the circuit layer. The encapsulant is disposed on the first redistribution structure and encapsulates the semiconductor die.

Package structure and manufacturing method thereof

A package structure including a substrate, a first semiconductor element disposed on and electrically connected with the substrate, a second semiconductor element disposed on and electrically connected with the substrate and a molding layer disposed over the substrate and covering at least a top surface of the substrate. The second semiconductor element and the first semiconductor element perform different functions. The molding layer encapsulates the second semiconductor element and wraps around sidewalls of the first semiconductor element. A top surface of the molding layer is higher than a top surface of the first semiconductor element. The molding layer has an opening extending from the top surface of the molding layer to the top surface of the first semiconductor element, so that the top surface of the first semiconductor element is exposed.

Growing community of inventors

Hsinchu, Taiwan

Ching-Hua Hsieh