Powerchip Semiconductor Corporation

Powerchip Technology Corporation

Powerchip Semiconductor Manufacturing Corporation

Ching-Hua Chen

Chun-Cheng Chen

Chan-Ching Lin

Chen-Hao Huang

Tzung-Bin Huang

Chen-Chiu Hsue

Jih-Wen Chou

Ming-Yuan Lin

Bing-Chen Ji

Han-Chao Lai

Yi-Chung Cheng

Shun-Tsung Yu

A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.

Non-volatile memory device and manufacturing method thereof

A method of fabricating a resistive random access memory (RRAM) device is disclosed. A plurality of word lines extending along a first direction are formed on a substrate with a recess between the word lines. A spacer-type resistance layer and a top electrode layer are formed on a sidewall of each of the word lines. A photoresist stripe pattern extending along a second direction is then formed on the substrate. The first direction is perpendicular to the second direction. An etching process is performed to remove the top electrode layer and the spacer-type resistance layer not covered by the photoresist stripe pattern to form a plurality of top electrodes. A diode is formed on each of the top electrodes.

Method for fabricating resistive random access memory

A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line.

Resistive random access memory and fabrication method thereof

First, a substrate having at least a conducting layer is provided. Then, a CVD process is performed to form the Ti/TiN barrier layer onto the conducting layer. An examination procedure is followed, and if particles are detected in the Ti/TiN barrier layer, then a rework procedure is performed to remove the Ti/TiN barrier layer and to reform a new Ti/TiN barrier layer.

Method of forming barrier layer

A method for forming a titanium nitride layer. A pre-heating step is performed, wherein a substrate is placed in a chamber comprising inert gas with a pre-heating pressure between 0.1&#x2dc;3 torr. A TiN deposition step is then performed, wherein the substrate is placed in a reactive gas at least comprising NHand TiCl, and the first TiN deposition step has a reactive pressure of more than 5 torr and a reactive temperature of more than 500&#xb0; C.

Method for forming a titanium nitride layer

A method of stabilizing the properties of a material layer is disclosed. A plurality of wafers are stored in a FOUP and in sequence the wafers are transferred to a chamber to proceed with deposition of a material layer and to the FOUP filled with a specific gas after deposition until all the wafers in the FOUP are treated. In the process of deposition, the wafers deposited with material layers on their surfaces are stored in the FOUP filled with specific gas. Therefore, the surface properties of all the wafers in the FOUP are stablilized and contamination due to outgassing is prevented.

Method of stabilizing material layer

A method for forming a titanium nitride layer. The method includes the steps of exposing a semiconductor substrate to a reactive gas containing TiCland NHfor a first deposition to form a layer of titanium nitride on the substrate, at reaction pressure less than 1 torr and temperature less than 500&#xb0; C.; placing the semiconductor substrate in NHgas for a first annealing step, at pressure between 1 and 3 torr; exposing the semiconductor substrate to a reactive gas comprising TiCland NHfor a second deposition, at pressure exceeding 5 torr and temperature exceeding 500&#xb0; C.; and subjecting the semiconductor substrate to a second annealing step in NHgas, at pressure exceeding 5 torr.

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Hsinchu, Taiwan

Ching-Hua Chen