Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Ching-Hsu Chang

Wen-Chun Huang

Ru-Gun Liu

Hung-Chun Wang

Cheng Kun Tsai

Feng-Ju Chang

Chun-Hung Wu

Ping-Chieh Wu

Nian-Fuh Cheng

Chih-Shiang Chou

Wen-Hao Liu

Feng-Lung Lin

Ming-Hsuan Wu

Ming-Hui Chih

Yu-Po Tang

Boren Luo

Wei-Chen Chien

Chi-Ping Liu

Wen Hao Liu

Chia-Feng Yeh

Jiann-Tyng Tzeng

Shih-Wei Peng

Chih-Min Hsiao

Chia-Lung Liu

Kuei-Li Huang

A method of generating an integrated circuit (IC) layout diagram includes obtaining a grid of intersecting first and second pluralities of tracks corresponding to adjacent metal layers, determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule, applying a via positioning pattern to the grid whereby via regions are restricted to alternating diagonal grid lines, positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines, and generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.

Diagonal via pattern and method

Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Optical proximity correction methodology using pattern classification for target placement

An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.

Method for integrated circuit manufacturing

Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.

The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.

Enhanced EUV lithography system

A home base station and method for supporting a plurality of cells under carrier aggregation. The home base station includes a preamble generator and a preamble monitor. The preamble generator allocates respective random access resources in the cells for handover to be carried out by a user equipment (UE), and upon receiving a handover request signal transmitted by a Mobility Management Entity (MME), generates a specific preamble and its transmission time, so that the UE performs random access on the cells based on the preamble and the transmission time to obtain the random access resources and sends out a Random Access Preamble (RAP). The preamble monitor enables the cells to simultaneously monitor the RAP sent by the UE, and when one of the cells receiving the RAP, identifies the cell on which the UE camps based on which one of the cells that has the RAP.

Home base station and method for supporting plurality of cells under carrier aggregation

An extreme ultraviolet photomask comprises a reflective layer over a substrate, a capping layer over the reflective layer, a hard mask layer over the capping layer, and an absorber. The absorber is in the hard mask layer, the capping layer and the reflective layer.

Extreme ultraviolet light (EUV) photomasks, and fabrication methods thereof

Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.

Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarizing process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber is substantially co-planar with the top surface of the hard mask layer.

Growing community of inventors

Taipei County, Taiwan

Ching-Hsu Chang