M31 Technology Corporation

Mediatek Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Lite-on It Corporation

High Tech Computer Corporation

Ching-Hsiang Chang

Yueh-Chuan Lu

Chun-Hung Lin

Sheng-Chi Chin

Ting-Hao Hsu

Yu-Ching Lee

Ching-Fang Yu

Yuan-Hsun Chang

Huai-Te Wang

Chun-Hsiang Lai

Hsi-Cheng Yeh

Cheng-Liang Hung

Chen-Yu Hsiao

Tao-Yen Wei

Yi-Shih Wang

Yu-Chun Peng

Yu-Hsun Chien

Ming-Ting Wu

Tzu-Hsun Tung

Li-Hung Chiueh

Yu Hsiang Chang

Chih-Chieh Yao

Man-Ju Lee

Pin-Hao Feng

A driver circuit includes a first output terminal, a first switch, a second switch, a third switch and a power source. The first output terminal is arranged for outputting a data output. The first switch is selectively coupled between the first output terminal and a power supply node according to a data input. The second switch is selectively coupled between the first output terminal and a first reference node according to the data input. The third switch is selectively coupled between the first reference node and a reference voltage. The power source is configured to selectively provide one of a supply voltage signal and a supply current signal to the power supply node. When the power source is configured to provide the supply voltage signal, the third switch is switched on. When the power source is configured to provide the supply current signal, the third switch is switched off.

Load circuit of amplifier and driver circuit for supporting multiple interface standards

A voltage regulator circuit includes a first amplifier, a second amplifier and a transistor. Respective first input terminals of the first and second amplifiers are coupled to a first reference voltage and a second reference voltage, respectively. A connection terminal of the transistor is coupled to a supply voltage. A control terminal of the transistor is selectively coupled to one of respective output terminals of the first and second amplifiers. When the control terminal of the transistor is coupled to the output terminal of the first amplifier, another connection terminal of the transistor is coupled to a second input terminal of the first amplifier to output a regulated voltage. When the control terminal of the transistor is coupled to the output terminal of the second amplifier, the another connection terminal of the transistor is coupled to a second input terminal of the second amplifier to output the regulated voltage.

Configurable voltage regulator circuit and transmitter circuit

An integrated circuit in a transmitter includes a multi-lane interface, N signal generating circuits, a lane selection circuit and a control circuit. The multi-lane interface has N lanes. M of the N signal generating circuits are configured to generate M clock signals respectively. (N-M) of the N signal generating circuits are configured to generate (N-M) data signals respectively. The lane selection circuit is configured to select M of the N lanes as M clock lanes by coupling the M clock signals to the M clock lanes respectively, and couple one of the (N-M) data signals to one of remaining (N-M) lanes, serving as (N-M) data lanes, according to a data select signal. The control circuit is configured to generate a data select signal according to a lane identifier of the one of the (N-M) lanes. The data select signal has a signal value mapping to the lane identifier.

Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver

A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.

Power management circuit and method for integrated circuit having multiple power domains

A clock and data recovery circuit includes a phase detector (PD), a phase frequency detector (PFD), a multiplexer circuit, a conversion stage and an oscillator. The PD detects a difference in phase between a data signal and an oscillating signal to generate a first set of error signals. The PFD detects a difference in phase and frequency between a reference clock signal and the oscillating signal to generate a second set of error signals. The multiplexer circuit selectively outputs the first set of error signals or the second set of error signals as a third set of error signals according to a selection signal. The conversion stage determines a set of gains according to the selection signal, and converts the third set of error signals with the set of gains to generate a set of input signals. The oscillator generates the oscillating signal according to the set of input signals.

Clock and data recovery circuit with proportional path and integral path, and multiplexer circuit for clock and data recovery circuit

An integrated circuit in a physical layer of a receiver is provided. The integrated circuit includes a multi-lane interface, a lane selection circuit and N sampling circuits. The multi-lane interface has N lanes. N is an integer greater than one. The lane selection circuit, coupled to the multi-lane interface, is configured to select M of the N lanes as M clock lanes, and output M signals on the M clock lanes respectively. M is a positive integer less than N. Remaining (N&#x2212;M) lanes serve as (N&#x2212;M) data lanes. The N sampling circuits are coupled to the multi-lane interface and the lane selection circuit. (N&#x2212;M) of the N sampling circuits are coupled to the (N&#x2212;M) data lanes respectively. Each of the (N&#x2212;M) sampling circuits is configured to sample a signal on one of the (N&#x2212;M) data lanes according to one of the M signals on the M clock lanes.

A physical layer circuit at a transmitter includes an encoding chain and a plurality of flip-flops. The encoding chain, including encoding units coupled in series, is configured to encode a plurality of symbols to generate a plurality of first wire states. The encoding units are arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively. A first encoding unit is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit. The flip-flops are arranged to receive and output the first wire states according to a clock signal, respectively. One of the flip-flops is coupled between the first encoding unit and the second encoding unit. The second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the flip-flops.

Encoding and decoding architecture for high speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof

A load circuit includes a first resistive element, a first transistor and a tristate control circuit. The first transistor has a first control terminal, a first connection terminal and a second connection terminal. The first connection terminal is coupled to to one of a first amplifier output terminal and a connection node through the first resistive element. The second connection terminal is coupled to the other of the first amplifier output terminal and the connection node. The tristate control circuit has a signal output terminal coupled to the first control terminal. When the signal output terminal is in the low impedance state, the first control terminal is arranged to receive a first control signal outputted from the signal output terminal. When the signal output terminal is in the high impedance state, the first control terminal is arranged to receive a second control signal different from the first control signal.

Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.

Pellicle for advanced lithography

A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.

Physical layer circuitry for multi-wire interface

A clock generation circuit arranged in a first system is disclosed. The clock generation circuit includes: a first dual-mode PLL, arranged for generating a first output clock in an integer-N mode or a fractional-N mode selectively, the first output clock being generated based on a first reference clock; and a second dual-mode PLL, arranged for generating a second output clock in an integer-N mode or a fractional-N mode selectively, the second output clock being generated based on the first output clock or a second reference clock selectively. Associated circuitries are also disclosed.

Clock generation circuit and associated circuitry

A reconfigurable pin-to-pin interface includes lane circuits and a reconfiguration circuit. A first lane circuit of the lane circuits obtains a first received signal by receiving a first input signal transmitted via a first lane. A second lane circuit of the lane circuits obtains a second received signal by receiving a second input signal transmitted via a second lane. When the second lane is used as one data lane and the first lane is used as one clock lane, the reconfiguration circuit redirects the first received signal to the second lane circuit for acting as an clock input of the second lane circuit. When the first lane is used as one data lane, the reconfiguration circuit blocks the first received signal from being redirected to the second lane circuit for acting as the clock input of the second lane circuit.

Reconfigurable pin-to-pin interface capable of supporting different lane combinations and/or different physical layers and associated method

A filter circuit includes an amplifier circuit, a resistor-capacitor (RC) network and a first voltage follower. The amplifier circuit has a first input terminal, a second input terminal and an output terminal. The amplifier circuit is configured to output a first output signal from the output terminal according to a first voltage signal at the first input terminal and a second voltage signal at the second input terminal. The RC network, coupled to the first input terminal, is configured to produce the first voltage signal at least in response to a first current signal applied to the first input terminal. The first voltage follower, coupled to the output terminal, is configured to receive the first output signal, and generate a first filtered signal in response to the first output signal.

Voltage regulator based loop filter for loop circuit and loop filtering method

An integrated circuit includes a first multi-lane interface having a plurality of first lanes, a second multi-lane interface having a plurality of second lanes; a first layer of clock lane selection units arranged to select one or two of the first and second lanes and output signals on the one or two selected lanes; a second layer of clock lane selection units arranged to select the one or two selected lanes as one or two clock lane and output signals on the one or two selected clock lane; and a plurality of sampling units, each coupled to second layer of clock lane selection units, each arranged to sample one of the first and second lanes according to the signal on the selected clock lane.

Integrated circuits adaptable to interchange between clock and data lanes for use in clock forward interface receiver

The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).

Growing community of inventors

Taipei, Taiwan

Ching-Hsiang Chang