Taiwan Semiconductor Manufacturing Comp. Ltd.

Ching-Hong Jiang

Clement Hsingjen Wann

Neng-Kuo Chen

Sey-Ping Sun

Gin-Chen Huang

Teng-Chun Tsai

Yung-Cheng Lu

Shen-Nan Lee

Kuo-Yin Lin

Te-Chien Hou

Ming-Shiuan She

Tsai-Fu Hsiao

Hongfa Luan

Huan-Chieh Su

Li-Ting Wang

Yi-An Lin

Cheng-Long Chen

Shih-Chiang Chen

An apparatus for performing chemical mechanical polish on a wafer includes a polishing head that includes a retaining ring. The polishing head is configured to hold the wafer in the retaining ring. The retaining ring includes a first ring having a first hardness, and a second ring encircled by the first ring, wherein the second ring has a second hardness smaller than the first hardness.

CMP polishing head design for improving removal rate uniformity

A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.

Fin structure of FinFET

An integrated circuit structure includes a semiconductor substrate, which includes a semiconductor strip. A Shallow Trench Isolation (STI) region is on a side of the semiconductor strip. The STI region includes a first portion comprising an oxide and a second portion free from oxide. The second portion separates the first portion from the semiconductor substrate. A semiconductor fin is over and aligned to the semiconductor strip, wherein the semiconductor fin is higher than a top surface of the STI region.

FinFETs with nitride liners and methods of forming the same

Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

Semiconductor device manufacturing methods and methods of forming insulating material layers

An embodiment method includes forming a first fin and a second fin over a semiconductor substrate. The first fin includes a first semiconductor strip of a first type, and the second fin includes a second semiconductor strip of the first type. The method further includes replacing the second semiconductor strip with a third semiconductor strip of a second type different than the first type. Replacing the second semiconductor strip includes masking the first fin using a barrier layer while replacing the second semiconductor strip and performing a chemical mechanical polish (CMP) on the third semiconductor strip using a slurry that planarizes the third semiconductor strip at a faster rate than the barrier layer. In some embodiments, the method may further include depositing a sacrificial layer over a wafer containing the first and second fins and performing a non-selective CMP to substantially level a top surface of the wafer.

High mobility devices and methods of forming same

An embodiment method includes forming a nanowire extending upwards from a substrate, wherein the nanowire includes: a bottom semiconductor region; a middle semiconductor region over the bottom semiconductor region; and a top semiconductor region over the middle semiconductor region. The method also includes forming a dielectric layer around and extending over the nanowire and forming a chemical mechanical polish-stop (CMP-stop) layer within the dielectric layer using an implantation process. After forming the CMP-stop layer, the dielectric layer is planarized.

Vertical gate all around (VGAA) transistors and methods of forming the same

Fin structure of FinFet

A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.

Growing community of inventors

Hsin-Chu, Taiwan

Ching-Hong Jiang