Vanguard International Semiconductor Corporation

Ching-Ho Li

Shao-Chang Huang

Yeh-Ning Jou

Kai-Chieh Hsu

Li-Fan Chen

Chun-Chih Chen

Chih-Hsuan Lin

Chieh-Yao Chuang

Gong-Kai Lin

Hsien-Feng Liao

Ting-You Lin

Hwa-Chyi Chiou

Chien-Hsien Song

Hsiao-Ying Yang

Yu-Kai Wang

Chang-Min Lin

Chien-Wei Wang

Fu-Chun Tseng

Ting-Yu Chang

Chien-Chi Hsu

A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.

Voltage tracking circuits with low power consumption and electronic circuits using the same

An electrostatic discharge (ESD) protection circuit including a detection circuit, a voltage-divider element, and a discharge element is provided. The detection circuit is coupled between a first power line and a second power line. In response to an ESD event, the detection circuit enables a turn-on signal. The voltage-divider element is coupled between the first power line and a third power line and receives the turn-on signal. The discharge element is coupled between the second and third power lines. In response to the turn-on signal being enabled, the first discharge element discharges an ESD current.

Electrostatic discharge protection circuit

A voltage tracking circuit is provided and includes first and second P-type transistors and a voltage reducing circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The voltage reducing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage reducing circuit reduces a first voltage at the first voltage terminal by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to a second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit. The output voltage is generated at the output terminal.

Voltage tracking circuits and electronic circuits

A semiconductor structure including a substrate, a first well, a second well, a first doped region, a second doped region, a gate electrode, an insulating layer, a field plate, and a tunable circuit is provided. The first and second wells are formed on the substrate. The first doped region is formed in the first well. The second doped region is formed in the second well. The gate electrode is disposed over the substrate. The gate electrode, the first doped region, and the second doped region constitute a transistor. The insulating layer is disposed on the substrate and overlaps the gate electrode. The field plate overlaps the insulating layer and the gate electrode. The tunable circuit provides either a first short-circuit path between the field plate and the gate electrode, or a second short-circuit path between the field plate and the first doped region.

Semiconductor structure and operation circuit

The protection circuit includes a detection circuit and a discharge circuit. The detection circuit is coupled to first and second power bonding pads and detects whether an ESD event or an EOS event occurs at the first power bonding pad. The detection circuit controls a detection voltage on a detection node according to a detection result. The first and second power bonding pads belong to different power domains. The discharge circuit is coupled to the detection node and the first power pad. In response to the ESD event occurring at the first power bonding pad, the discharge circuit provides a discharge path between the first power bonding pad and a ground terminal according to the detection voltage. In response to the EOS event occurring at the first power bonding pad, the detection circuit activates a second discharge path between the first power bonding pad and the ground terminal.

Protection circuits

A protection circuit including a detection circuit, a current discharge element, a first transistor, and a second transistor is provided. The detection circuit is coupled between a first pad and a second pad to detect ESD events. In response to an ESD event, the detection circuit sets the detection signal to a predetermined level. The current discharge element is coupled between the first and second pads. In response to the detection signal being at the predetermined level, the current discharge element is turned on so that the ESD current passes through the current discharge element. The first transistor is coupled between a core circuit and the second pad. The second transistor is coupled between the first transistor and the second pad. In response to the detection signal being at the predetermined level, the second transistor is turned on to turn off the first transistor.

Protection circuit

An operating circuit is provided. A first N-type transistor determines whether to create an open circuit between a core circuit and a ground terminal according to the voltage level of a specific node. An electrostatic discharge (ESD) protection circuit is coupled between an input/output pad and the core circuit to prevent an ESD current from passing through the core circuit. The ESD protection circuit includes a detection circuit and a releasing element. The detection circuit determines whether there is an ESD event at the input/output pad and generates a first detection signal according to the detection of the ESD event at the input/output pad. The releasing element provides a release path according to the first detection signal to release the ESD current. A control circuit controls the voltage level of the specific node according to the first detection signal.

Operating circuit having ESD protection function

A semiconductor device includes a semiconductor substrate, a Schottky layer, a plurality of first doped regions, a plurality of second doped regions, a first conductive layer and a second conductive layer. The semiconductor substrate includes a first conductive type, and the Schottky layer is disposed on the semiconductor substrate. The first doped regions and the second doped regions include a second conductive type, and which are disposed within the semiconductor substrate. The first doped regions are in parallel and extended along a first direction, and the second doped regions are in parallel and extended along a second direction to cross the first doped regions, thereby to define a plurality of grid areas. The first conductive layer is disposed on the Schottky layer, and the second conductive layer is disposed under the semiconductor substrate.

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Hsinchu, Taiwan

Ching-Ho Li