Taiwan Semiconductor Manufacturing Comp. Ltd.

Ching-Hao Shaw

Li-Chun Tien

Subramani Kengeri

Chih Hung Wu

Charlie Chueh

Lee-Chung Lu

Ker-Min Chen

Cliff Hou

Chia-Lin Cheng

Wan-Pin Yu

A circuit includes a capacitor and a memory element. The capacitor includes a first conductive layer, a first terminal, and a second terminal. The first conductive layer includes a first plurality of bars extending along a first direction and parallel to one another, where two adjacent bars of the first plurality of bars have a first capacitance therebetween. The first terminal is coupled with a first bar of the two adjacent bars, and the second terminal is coupled with a second bar of the two adjacent bars. The memory element has an input coupled with the first terminal and an output coupled with the second terminal. The capacitor is configured to inhibit changing a logic state at the input of the memory element.

Circuit having capacitor coupled with memory element

Some embodiments are related to a mesh capacitor, which improves the SER FIT rate. In an embodiment, the capacitor is connected between an input and an output of a latch in a flip-flop, making the flip-flop harder to flip due to radiation (e.g., from neutrons and/or alpha particles). In some embodiments, the capacitor is built directly vertically on top of the flip-flop, saving chip layout areas.

Providing capacitors to improve radiation hardening in memory elements

An on-chip logic cell timing characterization circuit is provided. Also provided are a method of conducting setup/hold characterization on a sequential cell and a method of characterizing propagation delay on a logic cell. A sequential cell on which setup/hold time is to be characterized is formed in duplicate with one close to the other. A first clock signal is sampled at a transition of a second clock signal on one sequential cell, and a setup time is determined by a state transition in the output signal of the first sequential. The second clock signal is sampled at a transition of the first clock signal on the other sequential cell, and a hold time is determined by a state transition in the output signal of the second sequential cell.

Method and system for setup/hold characterization in sequential cells

An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.

Standard cell back bias architecture

Methods of supplying voltages to integrated circuits are provided. A high voltage VddH and/or a low voltage VddL can be supplied to a filler cell and routed to other cells. Each of the VddH and VddL is carried by one of a first voltage supply wire and a second voltage supply wire. A voltage routing wire routes desired voltage(s) to a filler cell. The first and the second voltage supply wires are preferably formed parallel to the voltage routing wire with their edges substantially aligned to the edges of the voltage routing wire. Vias are made to route the desire voltage. Also preferably, the first voltage supply wire is an Mwire formed outside the filler cell while the second voltage supply wire is an Mwire formed inside the filler cell.

Very fine-grain voltage island integrated circuit

Standard cell layout efficiency is improved by utilization of a MOS interconnect that minimizes features and geometries requiring compliance with space intensive design rules. Source diffusion regions of MOS structures have a substantially constant width extension extending toward a substrate pick-up diffusion and shares a common silicidation therewith to effect an ohmic contact thereto.

Growing community of inventors

Hsin-Chu, Taiwan

Ching-Hao Shaw