Marvell International Limited

Marvellworld Trade Ltd.

Mobilic Technology (cayman) Corp.

Ablaze Wireless, Inc.

Ching-Han Tsai

Li Sha

Chi-Kuang Chen

Guan-Ming Su

Yaojun Luo

Shuhua Xiang

Leung Chung Lai

Chengjun Wang

Cheng-Lun Chang

Tzun-Wei Lee

Jau-Wen Ren

Hongjie Guan

Ye Zhou

Junqiang Lan

Qian Tang

Lincheng Wang

Uma Shankar Durvasula

Wenchi Hsu

Haohong Wang

Jung-Tao Liu

Tao Xie

Ya-Chau Yang

Satish Kumar Vutukuri

In accordance with the teachings described herein, systems and methods are provided for advanced execution of branch instructions in a microprocessor pipeline. In one embodiment, a branch instruction of an assembly language program code is executed that includes (i) a condition operand, (ii) a branch destination operand, and (iii) a program count operand. It is determined whether a current program count matches a stored program count operand. After determining that a condition was met when the branch instruction was executed, and in response to determining that the current program count matches the stored program count operand, a destination instruction specified by the stored branch destination operand is fetched.

Early execution of conditional branch instruction with pc operand at which point target is fetched

Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.

Processing rasterized data

This disclosure describes tools capable of generating messages for use in deblocking filtering a video stream, the messages based on prediction parameters extracted from the video stream.

Deblocking filtering

Embodiments of the present invention provide graphic processing techniques and configurations including an apparatus comprising a storage medium having stored therein a table comprising information about respective positions and sizes of a number of rectangular blocks, the rectangular blocks to substantially form at least one plane having an arbitrary shape object, and at least one overlay engine operatively coupled with the table and associated with the at least one plane to request the information about the respective positions and the sizes of the number of rectangular blocks to provide graphics overlay of the arbitrary shape object. Other embodiments may be described and/or claimed.

Graphic processing techniques and configurations

Devices, systems, methods, and other embodiments associated with decoding image data are described. In one embodiment, an apparatus decoding a bitstream includes a parser that parses a command that includes instructions for decoding a syntax element bitstream from the bitstream. The parser functions to identify a number times to repeat the command and to identify a table associated with the syntax element bitstream based, at least in part, on a table identification (ID) in the command. A decoder decodes the syntax element bitstream as specified by the command based, at least in part, on retrieving a value in a table associated with the table ID to generate a syntax element.

Decoding image data

A system including a binarization module, a prediction module, and a shifting module. The encoding module is configured to encode symbols using context-adaptive binary arithmetic coding, in which the symbols are generated by binarizing a syntax element. The prediction module is configured to generate a prediction for a number of renormalizations to be performed to renormalize an interval range when encoding one of the symbols. The shifting module is configured to generate a renormalized interval range by shifting the binarized syntax element R times, where R is a number of leading zeros before a 1 in the binarized syntax element. The encoding module is configured to encode a next symbol following the one of the symbols based on the renormalized interval range.

Context-based adaptive binary arithmetic coding engine

In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in first out (FIFO) manner. The second interface is coupled between the random access memory and a processor, and operates in a random access manner. As a result, the processor is not required to be in the loop when data is being transferred between the random access memory and the storage devices.

System and method of video decoding using hybrid buffer

Devices, systems, methods, and other embodiments associated with a buffer controller are described. In one embodiment, an apparatus includes a buffer to buffer data. The apparatus further includes a status register and control logic. The control logic at least processes write commands. When the buffer is full and a write command to write data to the buffer is received, the control logic is configured to: accept the data without writing the data to the buffer, send an acknowledgment that the buffer was written, and set an overflow bit in the status register.

Buffer controller

An external memory based FIFO (xFIFO) apparatus coupled to an external memory and a register bus is disclosed. The xFIFO apparatus includes an xFIFO engine, a wDMA engine, an rDMA engine, a first virtual FIFO, and a second virtual FIFO. The xFIFO engine receives a FIFO command from the register bus and generates a writing DMA command and a reading DMA command. The wDMA engine receives the writing DMA command from the xFIFO engine and forwards an incoming data to the external memory. The rDMA engine receives the reading DMA command from the xFIFO engine and pre-fetches a FIFO data from the external memory. The wDMA engine and the rDMA engine synchronize with each other via the first virtual FIFO and the second virtual FIFO.

External memory based FIFO apparatus

In one embodiment the present invention includes a microprocessor that has a pipeline circuit, a branch circuit, and a control circuit. The pipeline circuit pipelines instructions for the microprocessor. The branch circuit is coupled to the pipeline circuit and operates to store branch information. The control circuit is coupled to the pipeline circuit and the branch circuit. The control circuit stores a first branch information from the pipeline circuit to the branch circuit when a first condition is met. The control circuit retrieves a second branch information from the branch stack circuit to the pipeline circuit when a second condition is met. In this manner, the need for dedicated pipeline flush circuitry is avoided.

Execution of conditional branch instruction specifying branch point operand to be stored in jump stack with branch destination for jumping to upon matching program counter value

A system including a binarization module, an encoding module, and a prediction module. The binarization module is configured to binarize a syntax element and to generate symbols. The encoding module is configured to encode the symbols using context-adaptive binary arithmetic coding (CABAC). The prediction module is configured to generate a prediction for a number of renormalizations to be performed to renormalize an interval range when encoding one of the symbols. The encoding module encodes a next symbol following the one of the symbols based on the prediction before renormalization of the interval range is actually completed.

Growing community of inventors

San Jose, CA, United States of America

Ching-Han Tsai