Advanced Semiconductor Engineering, Inc.

Other

Ching-Han Huang

Lu-Ming Lai

Yu-Hsuan Tsai

Chi Sheng Tseng

Hui-Chung Liu

Hsun-Wei Chan

Kuo-Hua Lai

Hsu-Liang Hsiao

An-Nong Wen

Cheng-Ling Huang

Ching-Ho Chang

Chia-Hung Shen

Ming Yen Lee

Chang Chin Tsai

Yu-Che Huang

Yung-Yi Chang

Tien-Hsi Lee

Chia-Hao Sung

Yao-Yu Yang

Yu-Min Peng

Hsin Lin Wu

Pu Shan Huang

Chia Hao Sung

Chao-Liang Chang

Chien-Wei Fang

Po-Ming Huang

The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component and a support component. The first electronic component is disposed on the substrate. The first electronic component has a backside surface facing a first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The backside surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.

Electronic package structure

At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate with a first groove and a semiconductor device. The first groove has a first portion, a second portion, and a third portion, and the second portion is between the first portion and the third portion. The semiconductor device includes a membrane and is disposed on the second portion of the first groove. The semiconductor device has a first surface adjacent to the substrate and opposite to the membrane. The membrane is exposed by the first surface.

Semiconductor device package and a method of manufacturing the same

A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.

Semiconductor package and method for manufacturing the same

Semiconductor package structure and method of manufacturing the same

A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.

Semiconductor package structures and methods of manufacturing the same

An optical package structure includes a substrate, an emitter, a first detector and a light-absorption material. The substrate has a first surface and a second surface opposite to the first surface, the substrate includes a via defining a third surface extending from the first surface to the second surface. The emitter is disposed on the first surface of the substrate. The first detector is disposed on the first surface and aligned with the via of the substrate. The light-absorption material is disposed on the third surface of the substrate.

Optical package structure and method of manufacturing the same

A semiconductor package structure includes an organic substrate having a first surface, a first recess depressed from the first surface, a first chip over the first surface and covering the first recess, thereby defining a first cavity enclosed by a back surface of the first chip and the first recess, and a second chip over the first chip. The first cavity is an air cavity or a vacuum cavity.

Semiconductor package structure

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.

Semiconductor package including cap layer and dam structure and method of manufacturing the same

The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.

Semiconductor device package and method of manufacturing the same

The present disclosure provides a package structure and a manufacturing method. The package structure includes a substrate, a cover, a conductive pattern, and a sensing component. The cover is disposed on the substrate. The cover and the substrate define an accommodation space. The conductive pattern includes a conductive line. The conductive line is disposed on an internal surface of the cover exposed by the accommodation space, and is electrically connected to the substrate. The sensing component is disposed on the internal surface of the cover, and is electrically connected to the conductive line.

MEMS package structure and manufacturing method thereof

A semiconductor package structure includes a substrate, a semiconductor die, a lid and a cap. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate. The cap is disposed on the lid. The substrate, the lid and the cap define a cavity in which the semiconductor die is disposed, and a pressure in the cavity is greater than an atmospheric pressure outside the cavity.

Semiconductor package with inner and outer cavities

A microelectromechanical systems package structure includes a first substrate, a transducer unit, a semiconductor chip and a second substrate. The first substrate defines a through hole. The transducer unit is electrically connected to the first substrate, and includes a base and a membrane. The membrane is located between the through hole and the base. The semiconductor chip is electrically connected to the first substrate and the transducer unit. The second substrate is attached to the first substrate and defines a cavity. The transducer unit and the chip are disposed in the cavity, and the second substrate is electrically connected to the transducer unit and the semiconductor chip through the first substrate.

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Kaohsiung, Taiwan

Ching-Han Huang