United Microelectronics Corp.

Worldwide Semiconductor Manufacturing Corporation

Ching-Fu Lin

Chen-Ming Huang

Hua-Chou Tseng

Ching-Ling Lin

Yi-Wen Chen

Ren-Peng Huang

Teng-Chi Yang

First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.

Method of fabricating semiconductor device

A method of measuring the thickness of an epitaxial layer is disclosed. The method is particularly useful in measuring the epitaxial layer with a doping concentration lower than or similar to the substrate on which the epitaxial layer is formed. The method uses a non-single crystal layer previously formed on the substrate before forming the epitaxial layer over the substrate so that the portion of the epitaxial layer on the non-single crystal layer will be polycrystal. To obtain the thickness of the epitaxial layer, thicknesses of the polycrystal layer and the non-single crystal layer as well as the thickness difference between the polycrystal layer plus the non-single crystal layer and the epitaxial layer are measured. The thickness of the epitaxial layer equals the result of the total thickness of the polycrystal layer plus the non-single crystal layer minus the thickness difference between the polycrystal layer plus the non-single crystal layer and the epitaxial layer.

Method of measuring thickness of epitaxial layer

A dielectric layer and a polishing stop layer are respectively formed over a substrate. A glue layer composed of titanium (Ti) is formed along the surface of the dielectric layer. The Ti layer serves as adhension promotion to the subsequent TiN layer. A titanium-nitride (TiN) layer is next formed on the Ti layer to act as a barrier layer. A tungsten layer is deposited on the TiN layer. An etching back step is carried to etch the tungsten layer, therby leaving the tungsten in the contact holes to form the tungsten plug. Non-metal or oxide CMP is used to removes tungsten residues and TiN/Ti layers and the CMP will stop on the polishing stop layer.

Method of forming a tungsten plug

A method for forming a self-aligned contact structure is disclosed based on an HDP-CVD (High-Density Plasma-Chemical Vapor Deposition) process. Initially, after a polysilicon layer and a metal layer are deposited and patterned on a wafer to fabricate a gate stack, an HDP-CVD process is employed to form a deposition layer to cover the patterned layers and wafer. A building of sharp ridges occurs over the gate stack. Next, a spacer deposition layer is then conformally deposited to cover the HDP-CVD deposition layer. An anisotropically etch process is then performed to etch the spacer deposition layer, wherein at least portions of the spacer deposition layer still covers top of the gate stack. Another anisotropically etch process is then performed to form the required contacts on the wafer. Because the HDP-CVD deposition layer on the gate structure is thick enough to protect the gate stack from etching, it is unnecessary to form the cap layer as conventionally.

Growing community of inventors

Taipei, Taiwan

Ching-Fu Lin