Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Inventec Appliances Corporation

Inventec Appliances (pudong) Corporation

Inventec Appliances (shanghai) Co., Ltd.

Inventec Appliances (nanchang) Corporation

Hon Hai Precision Industry Co., Ltd.

Dell Products Inc.

Ching Fu Chang

Hsin-Chieh Huang

Hsi-Kuei Cheng

Chih-Kang Han

Ming-Yen Chiu

Li-Chun Tien

Yi-Kan Cheng

Ken-Hsien Hsieh

Wen-Hao Chen

Wen-Ju Preet Yang

Pin-Dai Sue

Chin-Chang Hsu

Ting Yu Chen

Tsong-Hua Ou

Cheng-I Huang

Chin-Hsiung Hsu

Wen-Li Cheng

Wei-Chi Chen

Ming-Shing Chen

Hung Lung Lin

I-Yu Chen

Dai-Shui Ho

Ju-Nan Chang

Chien Lin Ho

Teh-Yuh Lee

Wei-Jung Hung

Houjin Guo

Chih-Han Chen

Chao-Hsien Wu

Fang-Sheng Chou

Chia-Hui Hwang

Lu-Ran Huang

Xue-Jiao Zhang

A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.

Package with tilted interface between device die and encapsulating material

A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

Info structure with copper pillar having reversed profile

An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.

Package structure and method of forming the same

The present invention provides a test key structure, the test key structure a substrate, a plurality of test key cells disposed on the substrate, wherein each test key cell includes a first gate structure arranged along a first direction (X-axis), a first diffusion region, a second diffusion region, a connection diffusion region and a share contact arranged along a second direction (Y-axis), wherein the first gate structure crosses over the first diffusion region to form a pull-up transistor (PU), the second gate structure crosses over the second diffusion region to form a pull-down transistor (PD), and wherein the plurality of share contacts and the plurality of connection diffusion regions of the plurality of test key cells are electrically connected to each other.

Test key structure

A semiconductor memory device includes a first inverter, a second inverter, a first and second inner access transistors, and a first and second outer access transistors. The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor (PL) and a second pull-down transistor, and the first inverter and the second inverter forms a latch circuit. The first and second inner access transistors and the first and second outer access transistors are electrically connected to the latch circuit, and channel widths of the second inner access transistor and the second outer access transistor are different from each other.

Semiconductor memory device

In accordance with embodiments of the present disclosure, an information handling system may include an enclosure for housing information handling resources of the information handling system, the enclosure having an antenna slot formed therein and formed from a material substantially different from that in which the remainder of the enclosure is formed and a circuit board mechanically coupled to the enclosure and proximate to the antenna slot, the circuit board comprising an antenna electrically coupled at two or more locations to the enclosure so as to form a loop antenna and the antenna positioned such that the antenna at least partially overlaps the antenna slot.

Systems and methods for transloop impedance matching of an antenna

Growing community of inventors

Taipei, Taiwan

Ching Fu Chang