Wistron Neweb Corporation

Realtek Semiconductor Inc.

Ching-Feng Huang

Yung-Jinn Chen

Yu-cheng Lo

Yu-Meng Yen

Tsung-Tsung Huang

Meng-Luen Lee

The present disclosure discloses a multi-core processing circuit having power-stabilizing test mechanism that includes a plurality of core-processing circuits arranged in an order and a self-test scheduling circuit. Each of the core-processing circuits includes a memory built-in self-test circuit. The self-test scheduling circuit receives a main activation signal to activate the memory built-in self-test circuit of one of the core-processing circuits every delay time in the order based on signal handshake to perform self-test, wherein one of the activated core-processing circuits has a largest average power draining amount in a predetermined range within the delay time.

Multi-core processing circuit and test method of the same having power-stabilizing test mechanism

An electronic device and a method for performing clock gating in the electronic device are provided. The electronic device includes at least one function circuit, a device under test (DUT) circuit and at least one gating circuit. The function circuit is configured to operate according to at least one primary clock, and the DUT circuit is configured to operate according to at least one secondary clock. In addition, the clock gating circuit is configured to control whether to enable the primary clock according to at least one primary enable signal, and control whether to enable the secondary clock according to the primary enable signal and a secondary enable signal.

Electronic device and method for performing clock gating in electronic device

An antenna switching system is provided. The system includes a radio frequency (RF) circuit for transmitting and receiving signals, a first antenna, a second antenna, a first switch, a first switch assembly, a second switch assembly, and a power divider. The first switch electrically connected to the RF circuit. The first switch assembly electrically connected between the first switch and the first antenna. The second switch assembly electrically connected between the first switch and the second antenna. The power divider electrically connected between the first switch and the first switch assembly and between the first switch and the second switch assembly. When the first switch is switched to the power divider, the signals are transmitted by the first antenna and the second antenna.

Antenna switching system

An antenna switching system is provided. The system includes a radio frequency (RF) circuit for transceiving signals, N antennas, a master switch, N switches, and N power dividers. The signals may be transmitted by one of the N antennas, or the signals are transmitted by the antennas of the N antennas.

A wireless communication device and a filter are provided. The filter has an input end and an output end and includes a first energy storage element, a first series resonant circuit, a second series resonant circuit, a first parallel resonant circuit and a second parallel resonant circuit. The first and the second series resonant circuits respectively have a first capacitor and a first inductor connected in series. The first and the second parallel resonant circuits respectively have a second capacitor and a second inductor connected in parallel. The first series resonant circuit and the first parallel resonant circuit are electrically connected in cascade between a first end of the first energy storage element and a ground, and the second series resonant circuit and the second parallel resonant circuit are electrically connected in cascade between a second end of the first energy storage element and the ground.

Growing community of inventors

Hsinchu, Taiwan

Ching-Feng Huang