Taiwan Semiconductor Manufacturing Comp. Ltd.

Ching-Feng Fu

Yu-Lien Huang

Huan-Just Lin

Guan-Ren Wang

Yu-Chan Yen

Chun-Hung Lee

Chia-Ying Lee

De-Fang Chen

Yun-Min Chang

Chih-Hsin Ko

Shih-Ting Hung

Che-Ming Hsu

Hui-Cheng Chang

Tsai-Jung Ho

Clement Hsingjen Wann

Harry-Hak-Lay Chuang

Bao-Ru Young

Wei Cheng Wu

Hsin-Chih Chen

Bor Chiuan Hsieh

Guan-Xuan Chen

Chia Ming Liang

Meng-Fang Hsu

Kong-Pin Chang

Fu-Sheng Li

Mei-Yun Wang

Fu-Kai Yang

Chen-Ming Lee

Chang-Yun Chang

I-Wen Wu

Peng Wang

Teng-Chun Tsai

Li-Ting Wang

Chih-Tang Peng

Cheng-Tung Lin

Ming-Huan Tsai

Yi-Chen Lo

Tsai-Chun Li

Cheng-Hua Yang

Yu-lien Huang

D T Lee

Shu-Wen Chen

A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

Semiconductor device having air spacers

A method includes forming a first inter-layer dielectric (ILD) layer over source and drain regions of a semiconductor structure; forming a first mask material over the first ILD layer; etching first openings in the first mask material; filling the first openings with a fill material; etching second openings in the fill material; filling the second openings with a second mask material; removing the fill material; and etching the first ILD layer using the first mask material and the second mask material as an etching mask to form openings in the first ILD layer that expose portions of the source and drain regions of the semiconductor structure.

Semiconductor device and method

In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

Semiconductor devices

In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

Semiconductor device isolation features

A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Fin field-effect transistor device having contact plugs with re-entrant profile

A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Gap patterning for metal-to-source/drain plugs in a semiconductor device

In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

Middle-of-line interconnect structure and manufacturing method

A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.

Field effect transistor device with air gap spacer in source/drain contact

An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.

A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.

Interconnect structures for semiconductor devices and methods of manufacturing the same

In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.

A method is provided for sealing a seam in a self-aligned contact (SAC) layer that is disposed on a gate of a semiconductor structure. The method includes depositing a filler in the seam to seal the seam.

Method for sealing a seam, semiconductor structure, and method for manufacturing the same

An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Self-aligned interconnect with protection layer

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Taichung, Taiwan

Ching-Feng Fu