Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Industrial Technology Research Institute

Ching-Fang Yu

Ting-Hao Hsu

Sheng-Chi Chin

Chun-Hung Lin

Yu-Ching Lee

Tsun-Hsu Chang

Hsin-Chang Lee

Anthony Yen

Shinn-Sheng Yu

Chia-Jen Chen

Ta-Cheng Lien

Pei-Cheng Hsu

Wen-Chuan Wang

Ping-Hsun Lin

Ching-Hsiang Chang

Chia-Ching Huang

Syh-Yuh Cheng

Chwung-Shan Kou

Kwo Ray Chu

Mei-Chun Lin

Chao-Ta Fan

Larry Roger Barnett

Hung-I Chang

Wei-Yuan Chiang

Ling-Chieh Tai

Mark Chang

An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.

Lithography method with reduced impacts of mask defects

An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.

EUV mask blank and method of making EUV mask blank

Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.

Pellicle for advanced lithography

The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.

A pellicle is disposed over a lithography mask. An acoustic wave generator is placed over the pellicle. The acoustic wave generator is configured to generate acoustic waves to cause the pellicle to vibrate at a target resonance frequency. A resonance detection tool is configured to detect an actual resonance frequency of the pellicle in response to the acoustic waves. One or more electronic processors are configured to estimate an age condition of the pellicle as a function of a shift of the actual resonance frequency from the target resonance frequency.

Pellicle aging estimation and particle removal from pellicle via acoustic waves

Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.

Method for integrated circuit fabrication

An extreme ultraviolet (EUV) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The EUV mask includes a low thermal expansion material (LTEM) substrate and a reflective multilayer (ML) disposed thereon. A capping layer is disposed on the reflective ML and a patterned absorption layer disposed on the capping layer. The pattern includes an antireflection (ARC) type pattern.

EUV mask and method for forming the same

A method of inspecting fabricated articles includes receiving a fabricated article to be inspected for defects, the fabricated article having a pattern thereon, and the pattern being based on a pattern design and creating a rule set for defining critical regions of the pattern as represented in the pattern design, the critical regions being regions in which defects are more likely to be found during inspection. The method also includes applying the rule set to the pattern design to identify a critical region of the pattern on the fabricated article and a non-critical region of the pattern on the fabricated article. Further, the method includes inspecting the non-critical region of the pattern on the fabricated article for defects at first resolution and inspecting the critical region of the pattern on the fabricated article for defects at a second resolution higher than the first resolution.

Method and apparatus for efficient defect inspection

A lithographic process will use a mask or photomask. The photomask includes a first material layer, the first material layer providing a first outer surface of the photomask. The photomask also includes a second material layer over the first material layer, the second material layer providing a second outer surface of the photomask. The two outer surfaces are substantially in parallel and a distance between the two outer surfaces along a first axis perpendicular to the two outer surfaces defines a thickness of the photomask. Also, the two outer surfaces are connected by a plurality of sides, at least one of the sides is not perpendicular to the two outer surfaces and the at least one of the sides provides substantial area for holding the lithographic photomask.

Lithographic photomask with inclined sides

A method of identifying defects including producing, with an imaging system, an original image of a fabricated article having a feature thereon, the feature having an intended height and extracting a contour image from the original image, the contour image having an outline of those portions of the feature having a height approximate to the intended height. The method also includes producing a simulated image of the article based upon the contour and creating a defect image based on the differences between the simulated image and the original image, the defect image including any portions of the feature having a height less than the intended height.

Method and apparatus for defect identification

The a polarized high-order mode electromagnetic wave converter and its coupling method, uses bifurcate structure to divide the input wave into two signals with the same amplitude but opposition phases, which are then inputted into a circular main waveguide through waveguide so that the input wave could convert into linearly polarized high-order mode in the main waveguide, and then undergo the polarization change conversion stage to convert the polarized wave into circularly polarized wave. The coupling method includes the electromagnetic wave bifurcate stage, mode conversion stage, and may combine with a polarization conversion stage. The TE21 coupler is tested with simulation computation and fabricated, and proved to product consistent results with the computer simulation. The coupler has features of high conversion efficiency, high mode purity, wide bandwidth, polarity control, and convenience in processing.

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Hsinchu, Taiwan

Ching-Fang Yu