Integrated Memory Technologies, Inc.

Ching Dong Wang

Ching-Shi Jenq

Ching-Shi Jeng

A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.

Method of manufacturing a scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate

Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate

A method for making a non-volatile memory cell having a select gate, a floating gate and a control gate of the completely self-aligned type, partially self-aligned type and non-aligned type is disclosed. Further, each of the three types of cells has a floating gate, whose linear dimension can be increased beyond the smallest lithographic feature of the process design rule

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Cupertino, CA, United States of America

Ching Dong Wang