Taiwan Semiconductor Manufacturing Comp. Ltd.

Ching-Chung Su

Jiech-Fun Lu

Hung-Wen Hsu

Chia-Shiung Tsai

Yeur-Luen Tu

Shih-Pei Chou

Wei-Lin Chen

Shih-Chang Liu

Kuo-Cheng Lee

Chun-Hao Chou

Shih Pei Chou

Shu-Ting Tsai

Chun-Han Tsao

Yu-Lung Yeh

Keng-Ying Liao

Su-Yu Yeh

Jian Yuan Wu

Ming-Chi Wu

Po-Zen Chen

Chi-Yuan Wen

Chia-Chieh Lin

Chun-Chieh Fang

Che-Hsiang Hsueh

Dun-Nian Yaung

Jen-Cheng Liu

Wen-De Wang

Chung-Bin Tseng

Ching-Sheng Chu

Yen-Jou Wu

Jung-I Lin

Chih Wei Sung

Yu-Cheng Tsai

Meng-Hsien Lin

Guan-Hua Chen

Yi-Wei Chiu

Cheng-Hsien Chou

Yi-Shin Chu

Wen-I Hsu

Pin Chia Su

Kuo-Hsiu Wei

Chun-Tsung Kuo

Huai-jen Tung

Chih-Cherng Jeng

Chun-wen Cheng

Wei-Chuang Wu

Yih Song Chiu

Lin Chia-Chieh

Tzu Chan Weng

Jung-huei Peng

S Y Chen

An optical device includes a substrate, a first electrode, a second electrode, and a first lens. The first electrode and the second electrode are over the substrate and configured to generate a first electric field. The first lens is between the first electrode and the second electrode and has a focal length that varies in response to the first electric field applied to the first lens.

Optical device and method of manufacturing the same

A grid structure in a pixel array may be at least partially angled or tapered toward a top surface of the grid structure such that the width of the grid structure approaches a near-zero width near the top surface of the grid structure. This permits the spacing between color filter regions in between the grid structure to approach a near-zero spacing near the top surfaces of the color filter regions. The tight spacing of color filter regions provided by the angled or tapered grid structure provides a greater surface area and volume for incident light collection in the color filter regions. Moreover, the width of the grid structure may increase at least partially toward a bottom surface of the grid structure such that the wider dimension of the grid structure near the bottom surface of the grid structure provides optical crosstalk protection for the pixel sensors in the pixel array.

Grid structure with at least partially angled sidewalls

A pixel sensor may include a layer stack to reduce and/or block the effects of plasma and etching on a photodiode and/or other lower-level layers. The layer stack may include a first oxide layer, a layer having a band gap that is approximately less than 8.8 electron-Volts (eV), and a second oxide layer. The layer stack may reduce and/or prevent the penetration and absorption of ultraviolet photons resulting from the plasma and etching processes, which may otherwise cause the formation of electron-hole pairs in the substrate in which the photodiode is included.

Pixel sensor including a layer stack to reduce and/or block the effects of plasma processing and etching on the pixel sensor

An image sensor includes a first photodiode and a second photodiode. The image sensor further includes a first color filter over the first photodiode; and a second color filter over the second photodiode. The image sensor further includes a first microlens over the first color filter and a second microlens over the second color filter. The image sensor further includes a first electro-optical (EO) film between the first color filter and the first microlens, wherein a material of the first EO film is configured to change refractive index in response to application of an electrical field. The image sensor further includes a second EO film between the second color filter and the second microlens, wherein a material of the second EO film is configured to change refractive index in response to application of an electrical field.

Image sensor and method of making

The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

High capacitance MIM device with self aligned spacer

A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

BSI chip with backside alignment mark

Various embodiments of the present disclosure are directed towards a semiconductor structure including a photodetector disposed within a substrate. A grid structure is disposed over the substrate and the photodetector. A conductive layer is disposed between the grid structure and the substrate. A conductive contact extends into an upper surface of the substrate. The conductive layer is directly electrically coupled to the conductive contact.

Charge release layer to remove charge carriers from dielectric grid structures in image sensors

The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. The substrate has a plurality of protrusions disposed along a first side of the substrate over the image sensing element and a ridge disposed along the first side of the substrate. The ridge continuously extends around the plurality of protrusions.

Absorption enhancement structure for image sensor

Various embodiments of the present disclosure are directed towards a method for manufacturing a semiconductor structure. The method includes forming photodetectors within a semiconductor substrate. A charge release layer is deposited over the semiconductor substrate. A conductive contact is formed over the charge release layer such that a contact protrusion of the conductive contact extends through the charge release layer. The charge release layer is disposed along opposing sidewalls of the conductive contact. The charge release layer is electrically coupled to ground via the conductive contact.

The present disclosure describes the formation of a pad structure in an image sensor device using a sacrificial isolation region and a silicon oxide based stack with no intervening nitride etch-stop layers. The image sensor device includes a semiconductor layer comprising a first horizontal surface opposite to a second horizontal surface; a metallization layer formed on the second horizontal surface of the semiconductor layer, where the metallization layer includes a dielectric layer. The image sensor device also includes a pad region traversing through the semiconductor layer from the first horizontal surface to the second horizontal surface. The pad region includes an oxide layer with no intervening nitride layers formed on the dielectric layer of the metallization layer and a pad structure in physical contact with a conductive structure of the metallization layer.

Image sensor with pad structure

Various embodiments of the present disclosure are directed towards an image sensor including a charge release layer. A photodetector is disposed within a semiconductor substrate. An etch stop layer overlies the photodetector. A color filter overlies the etch stop layer. A dielectric grid structure surrounds the color filter. The charge release layer is sandwiched between the dielectric grid structure and the etch stop layer. The charge release layer surrounds the color filter and comprises a conductive material. The charge release layer directly contacts the color filter.

An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.

3DIC interconnect apparatus and method

Growing community of inventors

Tainan, Taiwan

Ching-Chung Su