United Microelectronics Corp.

Ching-Chun Hwang

Yuan-Li Tsai

Wei-Chung Chen

Meng-Jin Tsai

Chien-Kuo Yang

Sheng-Hsiung Yang

Kai-Jen Ko

Marcus Yang

Ralph Chen

Steven Huang

Ming-Hui Wu

Heng-Chun Kao

Fei-Hung Chen

A method for reducing a gate length bias is disclosed. The method utilizes an additional blanket ion implantation process to adjust the etching property of the undoped conductive layer. According to the present invention, a polysilicon layer is used to form NMOS and PMOS gate electrodes so that the gate length bias between the NMOS gate electrodes and the PMOS gate electrodes can be effectively reduced.

Method for reducing gate length bias

The method for forming high voltage device combined with a mixed mode process use an un-doped polysilicon layer instead of the conventional polysilicon layer. In the high resistance area, the ion implant is not used until the source region and the drain region are formed. A resistor is formed by etching oxide-nitride-oxide layer and performing ion implant process by using BF radical to the un-doped polysilicon layer to control the resistance. Then multitudes of contact are formed, wherein the high dosage of BF implant would reduce resistance between contacts and resistor.

Method for forming high resistance resistor with integrated high voltage device process

A method for forming enhanced field oxide (FOX) region of low voltage devices in a high voltage process is disclosed. The method includes providing a semiconductor structure comprising a substrate, two field oxide regions on the substrate, a well between the two field oxide regions in the substrate and a silicon nitride layer between the two field oxide regions above the well. As a key step, nitrogen is implanted into the semiconductor structure, and the silicon nitride layer is then removed. Then, a gate oxide layer on the well and silicon oxynitride layer on the field oxide regions are all formed in-situ.

Method for forming enhanced FOX region of low voltage device in high voltage process

A method for producing self-aligned silicidation, substantially facilitating the integration of the high-voltage and low-voltage MOS device, is disclosed. The method includes providing, the present invention provides a integration of high-voltage and low-voltage MOS transistor, which self-aligned silicidation process. A substrate is provided incorporating a device, wherein the device is defined high-voltage MOS region and low-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxide is spaced from another of the field oxide by a MOS region. Moreover, a polysilicon layer is formed over said high-voltage MOS region and low-voltage MOS region, and a first dielectric layer is deposited above the polysilicon layer of the high-voltage MOS region and low-voltage MOS region. Consequently, a first photoresist layer is formed over the first dielectric layer, wherein defining and etching the first photoresist layer to form gates of high-voltage MOS and low-voltage MOS. Then, using said second photoresist layer as a mask above low-voltage MOS region, firstly implanting the substrate of the high-voltage MOS region to form conductivity-type grade therein, and then the second photoresist layer of low-voltage MOS region is removed. Moreover, spacers are formed on sidewall of said gates of high-voltage MOS and low-voltage MOS, and then a second dielectric layer is formed on the substrate of high-voltage and low-voltage MOS.

Method for producing a high-voltage and low-voltage MOS transistor with salicide structure

A method for forming bipolar junction transistor with high gain via formulation of high voltage device in deep submicron process is disclosed. A substrate including a first part, a second part, and a third part is primarily provided; then, a first well in the first part and a second well in the second part are formed. A plurality of field oxide regions are formed on said substrate; subsequently, two third wells are formed in said third part. The following steps are to form a fourth well in said first well in said first part and two fifth wells in said second well in said second part; and to form a first gate on said first part between said two third wells, and a second gate on said second part between said two fifth wells. Next, a first spacer against said first gate and a second spacer against said second gate are formed. Further, first ions are introduced into said first part to serve as a collector region, and into said third part to serve as a first source/drain region. Finally, second ions are introduced into said first part to form an emitter region and a base region of a bipolar junction transistor, and into said second part to form a second source/drain region.

Growing community of inventors

Taichung, Taiwan

Ching-Chun Hwang